Full chip leakage estimation considering power supply and temperature variations

Su, Haihua; Liu, Frank; Devgan, Anirudh; Acar, Erdem; Nassif, Sani

doi:10.1145/871528.871529

Cited by 73 publications

(100 citation statements)

References 0 publications

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“…In our experiments we use a die thickness is 0.2mm. To account for CPU cores leakage power temperature dependency, we used the second-order polynomial model that is proposed in [19]. We extracted the model coefficients empirically based on the given normalized leakage values.…”

Section: A Methodologymentioning

confidence: 99%

Cool and save: Cooling aware dynamic workload scheduling in multi-socket CPU systems

Ayoub¹,

Rosing²

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Traditionally CPU workload scheduling and fan control in multi-socket systems have been designed separately leading to less efficient solutions. In this paper we present Cool and Save, a cooling aware dynamic workload management strategy that is significantly more energy efficient than state-of-the art solutions in multi-socket CPU systems because it performs workload scheduling in tandem with controlling socket fan speeds. Our experimental results indicate that applying our scheme gives average fan energy savings of 73% concurrently with reducing the maximum fan speed by 53%, thus leading to lower vibrations and noise levels.

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Section: A Methodologymentioning

confidence: 99%

Cool and save: Cooling aware dynamic workload scheduling in multi-socket CPU systems

Ayoub¹,

Rosing²

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…Due to 3D stack structure, the heat generated by the heat sources must flow through the body of the 3D tiers, and end at the environment interface (ambient) where it is spread through natural convection. Then, the heat flow inside this structure is diffusive in nature and hence, is modeled by its equivalence to an electronic RC circuit [8][9][10]. This is done by first dividing the entire structure into small cubical thermal cells as shown in Figure 2a.…”

Section: D Stack Thermal Modelmentioning

confidence: 99%

Through Silicon Via-based Grid for Thermal Control in 3D Chips

Ayala¹,

Sridhar²,

Pangracious³

et al. 2012

Design Technology for Heterogeneous Embedded Systems

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Abstract. 3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communication is the 3D integration technology and the use of through-silicon vias (TSVs) for inter-layer communication. However, 3D chips present important ther-mal issues due to the presence of processing units with a high power density, which are not homogeneously distributed in the stack. Also, the presence of hot-spots creates thermal gradients that impact negatively on the system reliability and relate with the leakage power consumption. Thus, new approaches for thermal control of 3D chips are in great need. This paper discusses the use of a grid and non-uniform placement of TSVs as an effective mechanism for thermal balancing and control in 3D chips. We have modelled the material layers and TSVs mathematically using a detailed calibration phase based on a real 5-tier 3D chip stack, where several heaters and sensors are manufactured to study the heat diffusion. The obtained results show interesting conclusions about thermal dissipation for 3D chips with TSVs and outline new insights in the area of thermal modeling and optimization for 3D chips by exploiting the inclusion of minimal percentages of TSVs in strategic positions of the layout.

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“…In recent years there has been an increasing interest to provide a detailed die temperature distribution [4,5]. In these works, the authors present different detailed full chip thermal models.…”

Section: Related Workmentioning

confidence: 99%

“…These positions are: close to the processing units (position 1), close to the memory devices (position 2), near the border of the chip (position 3) and surrounded by cooler devices (position 4) For every one of these placements, the thermal map of the register file is acquired supposing an homogeneous access pattern. Figure 6 shows these thermal maps.…”

Section: Optimization Policiesmentioning

confidence: 99%