FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC

Khodadadi, Elham; Barekatain, Behrang; Yaghoubi, Elham; Mogharrabi-Rad, Zahra

doi:10.1007/s11227-021-03906-1

Cited by 5 publications

(2 citation statements)

References 24 publications

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“…e traditional 3DMesh structure is a regular 3D network structure formed by stacking regular 2DNoCs up and down, and each layer realizes interlayer power communication through TSV. At present, most of the research on 3DNoC is based on this regular 3DMesh topology [1].…”

Section: Introductionmentioning

confidence: 99%

A Fault-Tolerant Structure for Nano-Power Communication Based on the Multidimensional Crossbar Switch Network

Luo

Liao

2022

International Transactions on Electrical Energy Systems

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In order to realize fault tolerance and further reduce the transmission delay, a fault-tolerant structure design method for nano-power communication based on a multidimensional crossbar switch network is proposed. The TSV router is designed as a double crossbar structure, namely the master crossbar (MasterCrossbar) and the slave crossbar (SlaveCrossbar). Each input port of the TSV router is divided into two subports. The port connected to the master crossbar has no input buffer, and the port connected to the slave crossbar has an input buffer. Master crossbar is the first choice for data transmission, and slave crossbar is selected when it is busy to reduce the transmission delay of data packets and reduce power consumption. Dual crossbar switches can also realize the fault tolerance of crossbar switches. The experimental results show that the author's fault-tolerant scheme, without incorporating the double crossbar switch, still has a much smaller transmission delay than the reference because the author realizes fault tolerance for defective TSVs by adding bidirectional TSVs to replace faulty TSVs. Therefore, when there is a TSV failure, the reference transmission delay increases with the number of failures, but the author's design allows packets to be transmitted in the network without being affected; the author's bidirectional TSV fault-tolerant design is combined with the double crossbar design. After that, the transmission delay is smaller than the original, and the maximum transmission delay is about 40% faster than the reference. The authors' design is superior and improves the reliability of the 3DNoC system.

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Section: Introductionmentioning

confidence: 99%

A Fault-Tolerant Structure for Nano-Power Communication Based on the Multidimensional Crossbar Switch Network

Luo

Liao

2022

International Transactions on Electrical Energy Systems

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“…Lee et al [11] proposed a multicast routing scheme that guarantees deadlock-free and improved throughput by using router marking rules, destination router partitioning, and traffic-adaptive branching, ultimately reducing the number of packet hops and dispersing channel traffic. Elham et al [12] developed a fault-tolerant routing algorithm (FT-PDC) based on path separation and congestion reduction for 3D NoC, which considers factors such as finding the shortest path, link failure, path diversity, and congestion. Alaei et al [13] proposed a multicast adaptive routing algorithm for Mesh networks based on fuzzy load control, which dynamically prevents live-lock and deadlock situations using a fuzzy control system, effectively reducing latency and congestion.…”

Section: Noc Routing Algorithmmentioning

confidence: 99%

TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures

Fang,

Wei,

Liu

et al. 2023

J Supercomput

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With the rapid development of heterogeneous network-on-chip (NoC), a vast amount of shared resources are integrated into NoC. Intense resource competition exists between CPUs and GPUs, leading to congestion and a decrease in overall network performance. Reasonable node placement can minimize network conflicts at the topology level. This paper first discusses the placement of shared last-level cache and memory controller, then selects a more rational placement method and optimizes the path. To solve the hot spots problem in center placement method, a task-based routing algorithm is designed to plan the path. Simulation results demonstrate that, compared to the traditional routing algorithm, the overall network latency is reduced by 9%, and the CPU performance is improved by 13.6%. Furthermore, a dynamic task-based routing algorithm is proposed. Compared to the static task routing algorithm, the overall network latency is reduced by 2.08%, and the CPU performance is improved by 4.09%.

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An efficient adaptive routing algorithm for the Co-optimization of fault tolerance and congestion awareness based on 3D NoC

Li,

Qin,

Sun

2023

Microelectronics Journal

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FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC

Cited by 5 publications

References 24 publications

A Fault-Tolerant Structure for Nano-Power Communication Based on the Multidimensional Crossbar Switch Network

A Fault-Tolerant Structure for Nano-Power Communication Based on the Multidimensional Crossbar Switch Network

TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures

An efficient adaptive routing algorithm for the Co-optimization of fault tolerance and congestion awareness based on 3D NoC

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