Proceedings of the 39th International Conference on High Energy Physics — PoS(ICHEP2018) 2019
DOI: 10.22323/1.340.0134
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Frontend and backend electronics for the ATLAS New Small Wheel Upgrade

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(3 citation statements)
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“…This sub-section presents the functional features of the ROC packet processing logic that were validated using the test setup on the ASIC prototypes. Together with the assessment of the output clock signals, forwarded TTC commands and their phase adjustment using oscilloscopes and logic analyzers, they assured the implementation correctness and allowed the development and implementation of the prototype boards used for integration tests (see [6] and [28]).…”
Section: Digital Design Validation Coveragementioning
confidence: 99%
“…This sub-section presents the functional features of the ROC packet processing logic that were validated using the test setup on the ASIC prototypes. Together with the assessment of the output clock signals, forwarded TTC commands and their phase adjustment using oscilloscopes and logic analyzers, they assured the implementation correctness and allowed the development and implementation of the prototype boards used for integration tests (see [6] and [28]).…”
Section: Digital Design Validation Coveragementioning
confidence: 99%
“…ART signals provided by 8 MMFE8 VMM chips are driven to the ART Data-Driver Card (ADDC); it deserializes the addresses from several VMMs, appends a 5-bit VMM geographical address, a Bunch Cross ID (BCID) timestamp and forwards the data packet to the MM Trigger Processor through optical fiber. A complete description of the NSW data and trigger chains is provided in [11][12][13].…”
Section: Jinst 15 C09019mentioning
confidence: 99%
“…For more information, the reader is also referred to a general NSWelectronicsrelated proceeding that was published by the writer on behalf of the ATLAS collaboration [79].…”
Section: Discussionmentioning
confidence: 99%