From simulink to SCADE/lustre to TTA

Caspi, Paul; Curic, Adrian; Maignan, Aude; Sofronis, Christos; Tripakis, Stavros; Niebert, Peter

doi:10.1145/780753.780754

Cited by 21 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We are concerned with the assessment of the correctness of implementations of Stateflow charts. A frequent approach to this problem is based on the verification of automatic code generators [4,27,13]. We propose an orthogonal approach based on the verification of implementations with respect to a model of the chart.…”

Section: Introductionmentioning

confidence: 99%

Refinement-based verification of sequential implementations of Stateflow charts

Miyazawa

Cavalcanti

2011

Electron. Proc. Theor. Comput. Sci.

View full text Add to dashboard Cite

Simulink/Stateflow charts are widely used in industry for the specification of control systems, which are often safety-critical. This suggests a need for a formal treatment of such models. In previous work, we have proposed a technique for automatic generation of formal models of Stateflow blocks to support refinement-based reasoning. In this article, we present a refinement strategy that supports the verification of automatically generated sequential C implementations of Stateflow charts. In particular, we discuss how this strategy can be specialised to take advantage of architectural features in order to allow a higher level of automation.

show abstract

Section: Introductionmentioning

confidence: 99%

Refinement-based verification of sequential implementations of Stateflow charts

Miyazawa

Cavalcanti

2011

Electron. Proc. Theor. Comput. Sci.

View full text Add to dashboard Cite

show abstract

A Synchronous Language at Work: The Story of Lustre

Gnesi¹,

Margaria²

2012

Formal Methods for Industrial Critical Systems

View full text Add to dashboard Cite

The Real‐Time Systems Compiler: migrating event‐triggered systems to time‐triggered systems

Scheler

Schröder-Preikschat

2011

Softw Pract Exp

View full text Add to dashboard Cite

SUMMARY In this paper, we present a prototype of the Real‐Time Systems Compiler (RTSC). The RTSC is a compiler‐based tool that enables the migration from event‐triggered to time‐triggered real‐time systems. This is achieved by replacing the real‐time systems architecture of a given real‐time system. The real‐time systems architecture governs the structural properties of the white‐box view of a real‐time system: how are tasks attached to events and how are dependencies between different tasks implemented. The RTSC uses an abstraction called Atomic Basic Blocks (ABBs) to hide the real‐time systems architecture and capture all relevant dependencies of an event‐triggered system in a global ABB‐graph. The RTSC automatically extracts that ABB‐graph from an event‐triggered real‐time system given as source code, transforms that ABB‐graph appropriately, and maps it to a statically computed schedule that could be executed by standard time‐triggered real‐time operating systems. Important temporal properties of the physical environment of the real‐time system needed for that transformation are stored in a system model provided as additional input to the RTSC. Furthermore, we demonstrate the applicability of our approach and the operation of our prototype by transforming an event‐triggered control application into a time‐triggered equivalent. Copyright © 2011 John Wiley & Sons, Ltd.

show abstract

From simulink to SCADE/lustre to TTA

Cited by 21 publications

References 0 publications

Refinement-based verification of sequential implementations of Stateflow charts

Refinement-based verification of sequential implementations of Stateflow charts

A Synchronous Language at Work: The Story of Lustre

The Real‐Time Systems Compiler: migrating event‐triggered systems to time‐triggered systems

Contact Info

Product

Resources

About