From Java to FPGA: An Experience with the Intel HARP System

Caldeira, Pedro; Penha, Jeronimo Costa; Bragança, Lucas; Ferreira, Ricardo; Nacif, José Augusto M.; Ferreira, Renato; Pereira, Fernando Magno Quintão

doi:10.1109/cahpc.2018.8645951

Cited by 8 publications

(7 citation statements)

References 27 publications

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“…Note that the FPGA frequency for all the kernels is automatically determined by Intel's OpenCL compiler and ranges from 176 to 218 MHz. For all experiments we used the Java OpenJDK 1.8.0_131 64-Bits (C2 compiler) with the Java Virtual Machine Compiler Interface (JVMCI) 6 enabled and 16GB of Java heap memory.…”

Section: Methodsmentioning

confidence: 99%

“…Hardware Platforms TVM [26] static No No FPGA Pynq SoC MaxCompiler [25] dynamic No online Maxeler Platform Aparapi [34] dynamic No offline AMD GPUs, FPGAs Caldeira et al [6] dynamic Yes online Intel Harp FPGAs JOCL [20] dynamic No offline GPUs TornadoVM [12] dynamic No offline CPUs, GPUs, FPGAs TornadoVM + FPGA extensions dynamic Yes online, offline, emulation CPUs, GPUs, FPGAs…”

Section: Hls Comp Modementioning

confidence: 99%

“…Greaves and Singh [15] presented the Kiwi library that exposes various custom attributes to the programmers, and generates Verilog HDL from the C# input code. Caldeira, Penha, Braganca, Ferreira, Nacif, Ferreira, and Pereira [6] presented a framework that compiles Java programs into Verilog HDL. However, further interpolation is required to imprint the resulting Verilog code into the FPGA of Intel HARP platforms.…”

Section: Dynamic Fpga Code Generationmentioning

confidence: 99%

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Transparent Compiler and Runtime Specializations for Accelerating Managed Languages on FPGAs

Papadimitriou¹,

Fumero²,

Stratikopoulos³

et al. 2020

Programming

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In recent years, heterogeneous computing has emerged as the vital way to increase computers' performance and energy efficiency by combining diverse hardware devices, such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The rationale behind this trend is that different parts of an application can be offloaded from the main CPU to diverse devices, which can efficiently execute these parts as co-processors. FPGAs are a subset of the most widely used co-processors, typically used for accelerating specific workloads due to their flexible hardware and energy-efficient characteristics. These characteristics have made them prevalent in a broad spectrum of computing systems ranging from low-power embedded systems to high-end data centers and cloud infrastructures.However, these hardware characteristics come at the cost of programmability. Developers who create their applications using high-level programming languages (e.g., Java, Python, etc.) are required to familiarize with a hardware description language (e.g., VHDL, Verilog) or recently heterogeneous programming models (e.g., OpenCL, HLS) in order to exploit the co-processors' capacity and tune the performance of their applications. Currently, the above-mentioned heterogeneous programming models support exclusively the compilation from compiled languages, such as C and C++. Thus, the transparent integration of heterogeneous co-processors to the software ecosystem of managed programming languages (e.g. Java, Python) is not seamless.In this paper we rethink the engineering trade-offs that we encountered, in terms of transparency and compilation overheads, while integrating FPGAs into high-level managed programming languages. We present a novel approach that enables runtime code specialization techniques for seamless and high-performance execution of Java programs on FPGAs. The proposed solution is prototyped in the context of the Java programming language and TornadoVM; an open-source programming framework for Java execution on heterogeneous hardware. Finally, we evaluate the proposed solution for FPGA execution against both sequential and multithreaded Java implementations showcasing up to 224× and 19.8× performance speedups, respectively, and up to 13.82× compared to TornadoVM running on an Intel integrated GPU. We also provide a break-down analysis of the proposed compiler optimizations for FPGA execution, as a means to project their impact on the applications' characteristics. ACM CCS 2012Software and its engineering → Runtime environments;

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Section: Methodsmentioning

confidence: 99%

Section: Hls Comp Modementioning

confidence: 99%

Section: Dynamic Fpga Code Generationmentioning

confidence: 99%

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Transparent Compiler and Runtime Specializations for Accelerating Managed Languages on FPGAs

Papadimitriou¹,

Fumero²,

Stratikopoulos³

et al. 2020

Programming

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“…It provides the flexibility to the expert user for exploiting either socket or remote routine approach to establish connectivity to an FPGA. Bashir et al addressed the issue of poor utility and high computation complexity on high-dimensional data in [126] and proposed many network architectures for datacenters in [127,130,131].…”

Section: Cloud Servicesmentioning

confidence: 99%

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020

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Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

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“…Outro ponto é a complexidade das linguagens de desenvolvimento para descric ¸ão de hardware como Verilog e VHDL, que exige conhecimento do processo e da arquitetura do FPGA. Nos últimos anos, várias alternativas com código em alto nível vêm sendo propostas para simplificar esta etapa como, por exemplo, Java [Caldeira and et al 2018], OpenCL e o uso de diretivas de compilac ¸ão com a linguagem C++.…”

Section: Introduc ¸ãOunclassified

HPyC-FPGA - Integração de Aceleradores em FPGA de Alto Desempenho com Python para Jupyter Notebooks

Silva¹,

Penha²,

Ribeiro³

et al. 2022

Anais Do XXIII Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2022)

Self Cite

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O desenvolvimento de aceleradores em FPGAs (Field Programmable Gates Arrays) ainda é um desafio. Recentemente, o ambiente PYNQ da Xilinx possibilitou a integração de código Python com aceleradores em FPGA. A maioria dos exemplos está voltada para placas de prototipação utilizadas no desenvolvimento de aplicações embarcadas. Este artigo apresenta o algoritmo K-means de aprendizado de máquina não supervisionado como estudo de caso. A principal contribuição deste trabalho é o encapsulamento de 3 aceleradores acoplados com PYNQ usando o ambiente Jupyter Notebook. A avaliação foi realizada em uma máquina de alto desempenho utilizando um FPGA Alveo U55C com memória HBM (High Bandwidth Memory). Os resultados são promissores, além de mostrar as facilidades de uso do FPGA de forma encapsulada, o ganho de desempenho foi de uma a duas ordens de grandezas em comparação a um sistema com dois processadores Xeon(R) Silver 4210R com 10 núcleos cada, executando a etapa de classificação do algoritmo K-means.

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From Java to FPGA: An Experience with the Intel HARP System

Cited by 8 publications

References 27 publications

Transparent Compiler and Runtime Specializations for Accelerating Managed Languages on FPGAs

Transparent Compiler and Runtime Specializations for Accelerating Managed Languages on FPGAs

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

HPyC-FPGA - Integração de Aceleradores em FPGA de Alto Desempenho com Python para Jupyter Notebooks

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