Fringing Field Effect in MOS Devices

Pattanayak, D.N.; Poksheva, John G.; Downing, Robert; Akers, L.A.

doi:10.1109/tchmt.1982.1135931

Cited by 15 publications

(5 citation statements)

References 6 publications

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“…The divided gate voltage of gate edge (V G,E ) would be nearly equal to the divided gate voltage of gate center (V G,C ). Therefore, the entire gate electrode area entered into deep depletion region uniformly except gate edge due to the well-known edge fringing field effect (21). Fig.…”

Section: Resultsmentioning

confidence: 99%

Lateral Nonuniformity of the Tunneling Current of Al/SiO₂/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Hwu

2013

ECS Trans.

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Interesting area and perimeter dependency mechanisms of dark gate current in Al/SiO 2 /p-Si capacitor is demonstrated. To study this lateral non-uniformity phenomenon, three different thicknesses of top aluminum gate are intentionally designed to our capacitors. According to C-V and I-V measurements carried out in the dark, it is found that the device with thin top Al-gate will result in entirely different electrical characteristics compared with the device with thick top Al-gate. Moreover, measurements with light illumination show that there is enhanced edge charge collection efficiency in inversion due to edge fringing field effect.

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Section: Resultsmentioning

confidence: 99%

Lateral Nonuniformity of the Tunneling Current of Al/SiO₂/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Hwu

2013

ECS Trans.

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“…Hence, we perform not only a fundamental static performance analysis but also the related LF noise analysis. In the subthreshold region, a fringing field is formed near the sidewall of the SiNS [28,29], and 1/f 2 noise caused by interface traps of the sidewall is observed regardless of SiNS dimensions. Moreover, traps near the top (or bottom) interface mainly affect the electron carrier in the strong inversion region, resulting in the 1/f noise characteristics.…”

Section: Introductionmentioning

confidence: 99%

“…When W Real =165 nm, S ID in the strong inversion region showed a slight distortion of the flicker noise (1/f ) caused by the weak Lorentzian shape (1/f 2 ) component, whereas when W Real =85 nm, a more evident Lorentzian shape was observed. When a small gate voltage was applied before the device was turned on, the fringing field effect [28,29] at the SiNS sidewall in figure 3(c) created a large electric field on both sides of the SiNS channel compared to the top (or bottom) in the subthreshold region. Therefore, the sidewall traps (N it,side ) affected the current fluctuations before the top (or bottom) traps (N it,top ), the Lorentzian shape occurred before flicker noise in the subthreshold region before the device was turned on.…”

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confidence: 99%

Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET

Lee¹,

Kim²,

Lee³

et al. 2021

Nanotechnology

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Through time-dependent defect spectroscopy and low-frequency noise measurements, we investigate and characterize the differences of carrier trapping processes occurred by different interfaces (top/sidewall) of the gate-all-around silicon nanosheet field-effect transistor (GAA SiNS FET). In a GAA SiNS FET fabricated by the top-down process, the traps at the sidewall interface significantly affect the device performance as the width decreases. Compare to expectations, as the width of the device decreases, the subthreshold swing (SS) increases from 120 to 230 mV/dec, resulting in less gate controllability. In narrow-width devices, the effect of traps located at the sidewall interface is significantly dominant, and the 1/f 2 noise, also known as generation–recombination (G–R) noise, is clearly appeared with an increased time constant (τ i ). In addition, the probability density distributions for the normalized current fluctuations (ΔI D) show only one Gaussian in wide-width devices, whereas they are separated into four Gaussians with increased in narrow-width devices. Therefore, fitting is performed through the carrier number fluctuation-correlated with mobility fluctuations model that separately considered the effects of sidewall. In narrow-width GAA SiNS FETs, consequently, the extracted interface trap densities (N T ) distribution becomes more dominant, and the scattering parameter ( α S C ) distribution increases by more than double.

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“…Since we fellow the process to form the HfO 2 after finished our formation of interfacial layer (sample S), the reduced thickness of SiO 2 may be attributed to the annealing process after the formation of HfO 2 . Generally the edge fringing field effect 20 was commonly regarded as the drawback in novel devices or CMOS. 21 However, we want to deem this effect as advantage to gather more photo-excited carriers to effectively tunnel through oxide, which would be potential in integrating the CMOS image sensor 22 with non-complicated manufacturing process.…”

Section: Introductionmentioning

confidence: 99%

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

Pang

Hwu

2014

AIP Advances

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In this study, the current conduction mechanisms of structures with tandem high-k dielectric in illumination are discussed. Samples of Al/SiO2/Si (S), Al/HfO2/SiO2/Si (H), and Al/3HfO2/SiO2/Si (3H) were examined. The significant observation of electron traps of sample H compares to sample S is found under the double bias capacitance-voltage (C-V) measurements in illumination. Moreover, the photo absorption sensitivity of sample H is higher than S due to the formation of HfO2 dielectric layer, which leads to larger numbers of carriers crowded through the sweep of VG before the domination of tunneling current. Additionally, the HfO2 dielectric layer would block the electrons passing through oxide from valance band, which would result in less electron-hole (e−-h+) pairs recombination effect. Also, it was found that both of the samples S and H show perimeter dependency of positive bias currents due to strong fringing field effect in dark and illumination; while sample 3H shows area dependency of positive bias currents in strong illumination. The non-uniform tunneling current through thin dielectric and through HfO2 stacking layers are importance to MOS(p) tunneling photo diodes.

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Fringing Field Effect in MOS Devices

Cited by 15 publications

References 6 publications

Lateral Nonuniformity of the Tunneling Current of Al/SiO₂/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Lateral Nonuniformity of the Tunneling Current of Al/SiO₂/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

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Fringing Field Effect in MOS Devices

Cited by 15 publications

References 6 publications

Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

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Lateral Nonuniformity of the Tunneling Current of Al/SiO₂/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect

Lateral Nonuniformity of the Tunneling Current of Al/SiO₂/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect