Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications

Molina, M.C.; Ruiz-Sautua, R.; García-Repetto, P.; Hermida, R.

doi:10.1109/tcad.2008.2009140

Cited by 10 publications

(5 citation statements)

References 19 publications

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“…A combined execution of decomposition and pattern-matching techniques is applied on HLS problems, in order to reduce the total circuit area in [23]. The data path area is reduced by decomposing multi cycle operations, so that they are executed on monocycle functional units (FUs that take one clock cycle to execute and deliver their results).…”

Section: Related Workmentioning

confidence: 99%

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Dossis¹

2017

IRATJ

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Design environments and automated CAD systems are proliferated nowadays with various preferences and restrictions in their work environments. One serious problem of automated high-level synthesis tools is their inability of at least difficulty to use for low, bit level functions such as signal processing blocks. Here the Cubed-C environment is used for the rapid implementation of a number of low level functions and blocks such as UARTs without difficulty. Cubed-C is a full-strength high-level synthesis CAD system; nevertheless, its structure and properties make it particularly suitable for this type of fine-grained applications. The experiments in this paper prove that the Cubed-C synthesis tools are particularly suitable for both complex and for low, bit level signal coding functions.

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Section: Related Workmentioning

confidence: 99%

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Dossis¹

2017

IRATJ

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“…Complex control flow optimization has been evaluated in [2,11,12], but for small parts of code and by no means complete application tests [13], discusses synthesis for distributed logic and memory [14] uses communicating processes as a system specification medium. HLS methods that include memory access management are outlined in [1], where digital signal processing (DSP) and streaming applications are synthesized using performance constraints [15], analyses mutually exclusive scheduling on extended data-flow graphs (EDFG) [16] synthesizes behavioural descriptions with time constraints, where complex operations are decomposed into simpler ones, and a similar set of decomposed fragments of operators, with the same pattern, are scheduled in a clock cycle.…”

Section: Existing Work In Intelligent Hls Techniquesmentioning

confidence: 99%

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Dossis¹

2013

Adv Robot Autom

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The advancing complexity of contemporary microelectronics has motivated research in high-level and system synthesis (HLS). Formal and intelligent HLS techniques are presented in this contribution, thus the generated implementation is correct-by-construction. These intelligent techniques include RDF (Resource Description Framework) and logic relations, along with automatic implementation options and they are employed for the transformations of a hardware compiler. The proposed toolset utilizes compiler-generators, RDF rules and logic programming in combination with XML validation of the internal state of the compiler. These intelligent and formal techniques make the whole transformation from source code to implementation, formal. The HLS tool is enhanced with the Parallel, Abstract Resource -Constrained Scheduler, which aggressively optimizes the initial state schedules, into maximally parallelized ones. A number of custom options are applied by the user of this toolset, in order to automatically compile selected testcases from real-world applications which prove the usability of the embedded scheduler and the formal compilation of the intelligent HLS compiler. Synthesis of Custom Hardware from ADA with Artificial Intelligence TechniquesMichael Dossis* In [17] an actor, that is used to model every module or system process, communicates with other actors via communication channels. These actors are used by the System Co-Designer [17] to exercise electronic system level (ESL) design space exploration. In [18] the SURYA system utilises the Simplify theorem prover to prove that the RTL model generated by HLS tools is functionally-equivalent to the specification. SURYA found two bugs in the SPARK HLS tool [2], which were until then unknown. In [19] flip-flops are replaced with latches so as to improve implementation timing, since latches are inherently more tolerant to process variations than flip-flops. Nevertheless, latchbased design is more cumbersome than flip-flops. The W3C Resource Description FrameworkThe Resource Description Framework (RDF) is a metadata model and is used to model the information of web resources [7]. RDF models include subject-predicate-object relations with explicit statements, called triplets. Triplets specify resources that store knowledge, information and data retrieval in large automated software tools. This is achieved due to the suitability of RDF to capture, store, exchange, and use machine-readable web information. Here, RDF is used to formally model and validate the internal data and state of the author's HLS tool.The eXtensible Markup Language (XML) serialization format is used to define RDF. XML's syntax is formally specified [7] and is ideal to model simple triples such as subject-predicate-object (and other) relations. The following RDF relation: High-level Synthesis

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“…A combined execution of operation decomposition and pattern-matching techniques is targeted to reduce the total circuit area in (Molina et al, 2009). The datapath area is reduced by decomposing multicycle operations, so that they are executed on monocycle functional units (FUs that take one clock cycle to execute and deliver their results).…”

Section: Next Generation High-level Synthesis Toolsmentioning

confidence: 99%

High-Level Synthesis for Embedded Systems

Dossis¹

2012

Embedded Systems - Theory and Design Methodology

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Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications

Cited by 10 publications

References 19 publications

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

High-Level Synthesis for Embedded Systems

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