Frequency Scaled Green Data Flip Flop on Different Nanometer Technology Based FPGA

Kumar, Keshav; Pandey, Bishwajeet; Chaturvedi, Srishti Priya

doi:10.21058/gjecs.2019.41001

Cited by 2 publications

(2 citation statements)

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“…To promote the ideas of green communication researchers have implemented a power-efficient CU on Virtex and Spartan family's FPGA (Pandey, 2020). An energyefficient CU is designed by authors with the help of HSTL and HSUL I/O standard for green communication on 28nm Artix-7 FPGA devices (Kumar, Pandey, & Chaturvedi, 2019e). An energy-efficient instruction register is designed by authors for integrating the green communication on Virtex 4, Virtex 5, and Virtex 6 FPGA (Siddiquee et al, 2019).…”

Section: Introductionmentioning

confidence: 99%

Implementation of Power-Efficient Control Unit on Ultra-scale FPGA for Green Communication

Pandey¹,

Kumar²,

Batool³

et al. 2021

3C Tecnología

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Whole world is suffering from the problem of the energy crisis. This is happening because of the enormous growth of population and industries across the globe. Therefore the whole world is looking to adopt the concepts of green communication technologies and power/energy efficient devices. This work is just towards these technologies. In this work, a power-efficient Control Unit (CU) is designed and implemented on Kintex-7 Ultrascale FPGA. The simulation and power analysis of the control unit is done on VIVADO HLx Design Suite. The power analysis of control unit is observed for different frequency values and it is observed that as the frequency increases the total power consumption also increases. Hence the control unit is more suitable to operate at low frequency values in order to minimize the power consumption. Also, there is a 36% saving in total power consumption when we scale down the device operating frequency of the control unit from 5 GHz to 100 MHz.

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Section: Introductionmentioning

confidence: 99%

Implementation of Power-Efficient Control Unit on Ultra-scale FPGA for Green Communication

Pandey¹,

Kumar²,

Batool³

et al. 2021

3C Tecnología

Self Cite

View full text Add to dashboard Cite

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“…It was found that for lower clocks, data transfer was impractical. Power analysis was performed using Vertex-6, Spartan 3, and Spartan 6 FPGAs in [4] for various frequencies from 10MHz to 100MHz. It was concluded that the power dissipation was less at low frequency, and at high frequency, the power was high.…”

mentioning

confidence: 99%

Design and Implementation of Power-Efficient FSM based UART

Kamath

Mendez

Ramya

et al. 2022

J. Phys.: Conf. Ser.

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The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

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Frequency Scaled Green Data Flip Flop on Different Nanometer Technology Based FPGA

Cited by 2 publications

References 0 publications

Implementation of Power-Efficient Control Unit on Ultra-scale FPGA for Green Communication

Implementation of Power-Efficient Control Unit on Ultra-scale FPGA for Green Communication

Design and Implementation of Power-Efficient FSM based UART

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