Frequency-Multiplexed Array Digitization for MIMO Receivers: 4-Antennas/ADC at 28 GHz on Xilinx ZCU-1285 RF SoC

Akram, Najath; Madanayake, Arjuna; Pulipati, Sravan; Venkatakrishnan, Satheesh Bojja; Psychogiou, Dimitra; Volakis, John L.; Rappaport, Theodore S.; Marzetta, Thomas L.

doi:10.1109/access.2021.3120704

Cited by 4 publications

(2 citation statements)

References 29 publications

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“…The building block Thiran filters are IIR filters that cannot be pipelined further without specialized computer architecture techniques; for example, we will explore the scattered/structured look-ahead pipelining [ 51 ] for digital processors, which are based on complex pole-zero cancellations. The computer architectures arrived at by mapping the SFGs to pipelined parallel processors with Thiran twiddle filters will be implemented on an AMD-Xilinx RF-SoC platform, such as ZCU-1285/1275/111, and operated with RF front ends realized off chip to evaluate the multi-beam beamforming performance in a hardware-in-the-loop emulation [ 52 , 53 , 54 ].…”

Section: Future Workmentioning

confidence: 99%

Thiran Filters for Wideband DSP-Based Multi-Beam True Time Delay RF Sensing Applications

Perera,

Rathnasekara,

Madanayake

2024

Sensors

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The ability to sense propagating electromagnetic plane waves based on their directions of arrival (DOAs) is fundamental to a range of radio frequency (RF) sensing, communications, and imaging applications. This paper introduces an algorithm for the wideband true time delay digital delay Vandermonde matrix (DVM), utilizing Thiran fractional delays that are useful for realizing RF sensors having multiple look DOA support. The digital DVM algorithm leverages sparse matrix factorization to yield multiple simultaneous RF beams for low-complexity sensing applications. Consequently, the proposed algorithm offers a reduction in circuit complexity for multi-beam digital wideband beamforming systems employing Thiran fractional delays. Unlike finite impulse response filter-based approaches which are wideband but of a high filter order, the Thiran filters trade usable bandwidth in favor of low-complexity circuits. The phase and group delay responses of Thiran filters with delays of a fractional sampling period will be demonstrated. Thiran filters show favorable results for sample delay blocks with a temporal oversampling factor of three. Thiran fractional delays of orders three and four are mapped to Xilinx FPGA RF-SoC technologies for evaluation. The preliminary results of the APF-based Thiran fractional delays on FPGA can potentially be used to realize DVM factorizations using application-specific integrated circuit (ASIC) technology.

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Section: Future Workmentioning

confidence: 99%

Thiran Filters for Wideband DSP-Based Multi-Beam True Time Delay RF Sensing Applications

Perera,

Rathnasekara,

Madanayake

2024

Sensors

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“…To overcome the aforementioned challenge, a lowprofile aperture-in-aperture (AiA) realization is investigated, considering 3 classes of antennas: a) ultra-wideband (UWB) tightly coupled arrays (TCDAs) [91], [92] [93]- [96], b) low profile planar circular monopole [97], [98] [99]- [101], and c) UWB patches [102], [103]. [104], [105].…”

Section: B Compact Wideband Aperture In Aperture Antenna Arraysmentioning

confidence: 99%

Cellular Wireless Networks in the Upper Mid-Band

Kang,

Mezzavilla,

Rangan

et al. 2024

IEEE Open J. Commun. Soc.

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The upper mid-band -approximately from 7 to 24 GHz -has recently attracted considerable interest for new cellular services. This frequency range has vastly more spectrum than the highly congested bands below 7 GHz while offering more favorable propagation and coverage than the millimeter wave (mmWave) frequencies. In this regard, the upper mid-band has the potential to provide a powerful and complementary frequency range that balances coverage and capacity. Realizing cellular networks that exploit the full range of these bands, however, presents significant technical challenges. Most importantly, spectrum will likely need to be shared with incumbents including communication satellites, military RADAR, and radio astronomy. Also, the upper mid-band is simply a vast frequency range. Due to this wide bandwidth, combined with the directional nature of transmission and intermittent occupancy of incumbents, cellular systems will likely need to be agile to sense and intelligently use large spatial and frequency degrees of freedom. This paper attempts to provide an initial assessment of the feasibility and potential gains of such adaptive wideband cellular systems operating across the upper mid-band. The study includes: (1) a detailed ray tracing simulation to assess potential gains of multi-band systems in a representative dense urban environment and illustrate the value of a wideband system with dynamic frequency selectivity; (2) an evaluation of potential cross-interference between satellites and terrestrial cellular services and interference nulling to reduce that interference; and (3) design and evaluation of a compact multi-band antenna array structure. Leveraging these preliminary results, we identify potential future research directions to realize next-generation systems in these frequencies.

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RFSoC-FPGA Realization of a Code-Multiplexed Digital Receiver (CMDR) Using 1-ADC/Quad-Channel

Ullah,

Venkatakrishnan,

Volakis

2024

IEEE J. Microw.

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A 4-channel code-multiplexed digital receiver is presented for multiple-input-multiple-output (MIMO) applications targeting 5G millimeter-wave (mm-Wave) communications. The receiver employs a code-multiplexing (CM) topology where multiple channels are encoded with unique orthogonal Walsh-Hadamard codes and multiplexed into a single-channel for digitization. This approach overcomes the bottleneck of hardware complexity, cost, and power consumption in traditional multiplexing topologies by employing a single wideband analog-to-digital converter (ADC) to serve several channels. The article presents an end-to-end testbed to demonstrate the effectiveness of the proposed Code-Multiplexed Digital Receiver (CMDR) that consists of 1) ultrawideband (UWB) tightly-coupled dipole array (TCDA), 2) a custom-designed encoder circuit board (ECB), and 3) a Radio-Frequency System-on-Chip (RFSoC) fieldprogrammable gate array (FPGA) for encoding and decoding. The code sequences were generated at a maximum clock frequency of 400 MHz. Extensive experimental measurements were performed and test results were validated using performance metrics such as normalized mean square error (NMSE) and adjacent channel interference (ACI). Test results showed ACI of >20 dB, NMSE = -24.592 dB and little or no degradation in signal-to-noise ratio (SNR). To the best of our knowledge, this is the highest clock frequency and ACI value for hardware validation of channel multiplexing scheme reported in the literature.

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Frequency-Multiplexed Array Digitization for MIMO Receivers: 4-Antennas/ADC at 28 GHz on Xilinx ZCU-1285 RF SoC

Cited by 4 publications

References 29 publications

Thiran Filters for Wideband DSP-Based Multi-Beam True Time Delay RF Sensing Applications

Thiran Filters for Wideband DSP-Based Multi-Beam True Time Delay RF Sensing Applications

Cellular Wireless Networks in the Upper Mid-Band

RFSoC-FPGA Realization of a Code-Multiplexed Digital Receiver (CMDR) Using 1-ADC/Quad-Channel

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