Freeform mask optimization using advanced image based M3D inverse lithography and 3D-NAND full chip opc application

Feng, Yaobin; Song, Zhiyang; Guo, Mengqiu; He, Jun; Guo, Longxia; Xu, Gang; Liu, Sam; Liu, Jingjing; Hsu, Stephen; Peng, Austin; Yang, Andy; Gupta, Rachit; Lu, Junwei; Peng, Victor; Wang, Jun; Shi, Xiaolong; Liu, Leon; Howell, Rafael C.; Zhang, Cuiping; Li, Zero; Jia, Ningning

doi:10.1117/12.2297397

Cited by 1 publication

(3 citation statements)

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“…ASML Brion also introduced their freeform ILT engine with mask 3D models, and they have demonstrated it on a FLASH memory full-chip application. 121 Dr. Pearman from D2S also presented a fast mask 3D model for curvilinear ILT using DL. 122…”

Section: Litho Model For Iltmentioning

confidence: 99%

“…Inspired by many success stories of ML in a broad range of artificial intelligence applications, both industrial and academic researchers are now actively developing ML solutions for challenging problems in computational lithography, including ILT. [99][100][101]121,[138][139][140] One of the first papers applying DL to ILT is from ASML Brion. Their 2017 paper shows how they use their freeform ILT engine to train an ILT DL model using a convolutional neural network (CNN) (Fig.…”

Section: Applying Deep Learning To Iltmentioning

confidence: 99%

“…Such DL-based SRAF generation has been demonstrated in both DRAM and logic full-chip applications 100,101 and FLASH memory full-chip application. 121 While most research work has focused on using DL to accelerate ILT, Dr. Peng Liu from Synopsys showed DL can create ILT solutions all by itself, plus all models-including neural network-based 3D mask, imaging, and resist models-required for ILT. 139 He demonstrated a standalone mask synthesis flow that runs entirely on the TensorFlow ® ML platform with a reinforcement learning (RL) approach and GPU acceleration.…”

Section: Applying Deep Learning To Iltmentioning

confidence: 99%

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Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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Section: Litho Model For Iltmentioning

confidence: 99%