Framework for analog test coverage

Bhatta, Debesh; Mukhopadhyay, I.; Natarajan, Suriyaprakash; Goteti, Prashant; Xue, Bin

doi:10.1109/isqed.2013.6523653

Cited by 10 publications

(6 citation statements)

References 23 publications

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“…Techniques were presented in [6]- [8] to use HDL/models for regions where faults are not injected to reduce runtime. In [9] and [10], techniques were proposed to inject faults only for selected duration thereby reducing the overall simulation time.…”

Section: Enhanced Analog Fault Simulationmentioning

confidence: 99%

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

Devanathan

Balasubramanian

Parekhji

2015

2015 28th International Conference on VLSI Design

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With SOCs being increasingly designed for communication and embedded processing applications, the content of analog, mixedsignal (AMS) and RF components in them has increased. Large SOCs are often dominated by these components, which in turn also contribute to the overall incurred test time, attainable test quality and time required for silicon debug and characterisation. Existing test methods based on the use of specification based tests and use of design verification test-benches are increasingly difficult to adopt in such SOCs (as compared to standalone IP chips) since a large number of such modules and their interactions must be tested in the budgeted test time. The paper describes the practical use of fault simulation for AMS circuits to address the above issues. The main contributions of this paper are two-fold. (i) Enhancements are proposed to a commercially available analog fault simulation flow to handle specific SOC requirements of accuracy and speed, using smart management of models and/or fault lists across different fault conditions and fault sites. (ii) Efficient test generation methods targeting the analog -digital interface are built by identifying uncovered regions/operating modes of the circuit. These are novel extensions to the commercial analog EDA tools supporting regular fault simulation. Experiments are performed on industrial designs and benefits are highlighted. It is expected that such techniques will be increasingly required to be integrated into the design flows for mixed-signal SOCs.

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Section: Enhanced Analog Fault Simulationmentioning

confidence: 99%

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

Devanathan

Balasubramanian

Parekhji

2015

2015 28th International Conference on VLSI Design

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“…Analog faults can be classified as catastrophic (or gross) faults and parametric (or soft) faults [5]. Gross faults are typically caused by structural deformities, such as open and short circuits, while parametric faults are generally caused by variations of component parameter values outside of their tolerance range.…”

Section: Introductionmentioning

confidence: 99%

Analog Gross Fault Identification in RF Circuits Using Neural Models and Constrained Parameter Extraction

Viveros-Wacher

Rayas‐Sánchez

Brito‐Brito

2019

IEEE Trans. Microwave Theory Techn.

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The demand and relevance of efficient analog fault diagnosis methods for modern RF and microwave integrated circuits increases with the growing need and complexity of analog and mixed-signal circuitry. The well-established digital fault diagnosis methods are insufficient for analog circuitry due to the intrinsic complexity in analog faults and their corresponding identification process. In this work, we present an artificial neural network (ANN) modeling approach to efficiently emulate the injection of analog faults in RF circuits. The resulting meta-model is used for fault identification by applying an optimization-based process using a constrained parameter extraction formulation. A generalized neural modeling formulation to include auxiliary measurements in the circuit is proposed. This generalized formulation significantly increases the uniqueness of the faults identification process. The proposed methodology is illustrated by two faulty analog circuits: a CMOS RF voltage amplifier and a reconfigurable bandpass microstrip filter.

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“…Analog faults are categorized as catastrophic (or gross) faults and parametric (or soft) faults [5]. Gross faults are typically caused by structural deformities, such as open and short circuits, while parametric faults are generally caused by variations of component parameters outside of their tolerance range.…”

Section: Introductionmentioning

confidence: 99%

“…Gross faults are typically caused by structural deformities, such as open and short circuits, while parametric faults are generally caused by variations of component parameters outside of their tolerance range. Prior work has used these two types of basic fault models and pursued a fault injection methodology to capture the circuit behavior under faulty conditions [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction

Viveros-Wacher

Rayas-Sanchez

2018

2018 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO)

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The increase of analog and mixed-signal circuitry in modern RF and microwave integrated circuits demands for improved analog fault diagnosis methods. While digital fault diagnosis is well established, the analog counterpart is relatively much less mature due to the intrinsic complexity in analog faults and their corresponding identification. In this work, we present an artificial neural network (ANN) modeling approach to efficiently emulate the injection of analog faults in RF circuits. The resulting meta-model is used for fault identification by applying an optimization-based process using a constrained parameter extraction formulation. The proposed methodology is illustrated by a faulty analog CMOS RF circuit.

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Framework for analog test coverage

Cited by 10 publications

References 23 publications

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

Analog Gross Fault Identification in RF Circuits Using Neural Models and Constrained Parameter Extraction

Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction

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