FPM: A Flexible Programming Model for MPSoC on FPGA

Wang, Chao; Li, Xi; Zhang, Junneng; Chen, Peng; Feng, Xiaojing; Zhou, Xuehai

doi:10.1109/ipdpsw.2012.62

Cited by 13 publications

(4 citation statements)

References 11 publications

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“…In this article, MP-Tomasulo is based on a flexible programming framework FPM [Wang et al 2012], which is an extended version of CellSs [Bellens et al 2006] from CellBE to general FPGA architecture. FPM is a software-hardware codesign paradigm that contains both C compilers for software applications and also hardware generation design flows for the IP-based accelerator on FPGA platforms.…”

Section: Software/hardware Codesign Flowmentioning

confidence: 99%

“…Compared to Scoreboarding [Wang et al 2012], Tomasulo has higher scheduling overheads, which leads to a bigger gap between the experimental and theoretical value. However, since MP-Tomasulo cannot only detect WAW and WAR hazards but also eliminate them by renaming, the overall speedup is significantly larger than Scoreboarding.…”

Section: Speedup Of Mp-tomasulo Vsmentioning

confidence: 99%

“…Therefore, we have also realized a hardware scheduling module according to the data structures and processing flow described in Section 5. Along with the Scoreboarding technique [Wang et al 2012], there are also some creditable OoO execution engines, like [Gupta and Sohi 2011]. In order to evaluate its superiority, we use a JPEG application to test the efficiency of our framework.…”

Section: A Comparative Study On Jpeg Applicationsmentioning

confidence: 99%

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MP-Tomasulo

Wang

Zhang

et al. 2013

ACM Trans. Archit. Code Optim.

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This article presents MP-Tomasulo, a dependency-aware automatic parallel task execution engine for sequential programs. Applying the instruction-level Tomasulo algorithm to MPSoC environments, MPTomasulo detects and eliminates Write-After-Write (WAW) and Write-After-Read (WAR) inter-task dependencies in the dataflow execution, therefore to operate out-of-order task execution on heterogeneous units. We implemented the prototype system within a single FPGA. Experimental results on EEMBC applications demonstrate that MP-Tomasulo can execute the tasks out-of-order to achieve as high as 93.6% to 97.6% of ideal peak speedup. A comparative study against a state-of-the-art dataflow execution scheme is illustrated with a classic JPEG application. The promising results show MP-Tomasulo enables programmers to uncover more task-level parallelism on heterogeneous systems, as well as to ease the burden of programmers. ACM Reference Format:Wang, C., Li, X., Zhang, J., Zhou, X., and Nie, X. 2013. MP-Tomasulo: A dependency-aware automatic parallel execution engine for sequential programs.

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Section: Software/hardware Codesign Flowmentioning

confidence: 99%

Section: Speedup Of Mp-tomasulo Vsmentioning

confidence: 99%

Section: A Comparative Study On Jpeg Applicationsmentioning

confidence: 99%

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MP-Tomasulo

Wang

Zhang

et al. 2013

ACM Trans. Archit. Code Optim.

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“…Consequently, as programming models require more experiences from the programmers, the extension from instruction level scheduling algorithm to task level provides an alternate methodology to utilize MPSoC platform effectively [3]. Regarding tasks as abstract instructions, Scoreboarding and Tomasulo algorithm can be applied to task level.…”

Section: Introductionmentioning

confidence: 99%

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

Guo

Wang

Zhou

et al. 2013

2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications

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Out-of-order execution scheme is one of the most promising technologies for task level parallelization in MPSoC design paradigms. However, it still poses a significant challenge to efficiently analyze the inter-task dependencies. This paper applies a traditional instruction level Scoreboarding algorithm at the task level in two forms: dynamic and static. A heterogeneous MPSoC prototype has been developed on FPGA with state-of-the-art dynamic partial reconfigurable technologies. The leverage between static and dynamic scheduling using task dependency analysis is obtained. Experimental results demonstrated a trade-off for the two modalities.

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Instruction Extension and Generation for Adaptive Processors

Wang

Zhang

et al. 2014

Lecture Notes in Computer Science

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FPM: A Flexible Programming Model for MPSoC on FPGA

Cited by 13 publications

References 11 publications

MP-Tomasulo

MP-Tomasulo

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

Instruction Extension and Generation for Adaptive Processors

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