FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays

Wang, Xiaoyuan; Wu, Zhiru; Zhou, Pengfei; Iu, Herbert Ho Ching; Kang, Sung-Mo; Eshraghian, Jason K.

doi:10.1109/tcsi.2022.3141087

Cited by 9 publications

(4 citation statements)

References 44 publications

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“…Since slow switching speeds and resistance dissipation offset data density benefit, exploring compatible applications for memristor CMOS logic gates remains elusive. Wang et al 129 proposed a ternary memristor model and designed and implemented a memristor CMOS ternary 2-9-wire decoder, as shown in Fig. 13.…”

Section: Artificial Memristor Integrated Pixel Circuitsmentioning

confidence: 99%

Advances in pixel driving technology for micro-LED displays

Gao,

Zou,

Zhong

et al. 2023

Nanoscale

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Section: Artificial Memristor Integrated Pixel Circuitsmentioning

confidence: 99%

Advances in pixel driving technology for micro-LED displays

Gao,

Zou,

Zhong

et al. 2023

Nanoscale

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“…It is difficult to achieve multi-value effects with traditional dual-port memristors, and it requires additional circuit consumption when designing large-scale memristor arrays. 19,20 In Zhang et al, 21 it was demonstrated that quantized current was a result of formation of tree-shaped conductive filaments inside the memristor with the SET/RSET process being controlled by the application of gate voltage. The electrical symbol of the gate-tunable memristor is shown in Figure 1A, and its approach to achieving multiple resistance states by applying different gate voltage to change its hysteresis loop is shown in Figure 1B.…”

Section: Proposed Model Of Gate-tunable Memristormentioning

confidence: 99%

“…With memristor arrays, more individual memristor resistance values enable higher quantization accuracy to be achieved. It is difficult to achieve multi‐value effects with traditional dual‐port memristors, and it requires additional circuit consumption when designing large‐scale memristor arrays 19,20 . In Zhang et al, 21 it was demonstrated that quantized current was a result of formation of tree‐shaped conductive filaments inside the memristor with the SET/RSET process being controlled by the application of gate voltage.…”

Section: Proposed Model Of Gate‐tunable Memristormentioning

confidence: 99%

A gate‐tunable memristor emulator for motion detection

Zhang,

Ma,

Shi

et al. 2023

Circuit Theory & Apps

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SummaryWith its low power consumption and small size, the memristor has shown great potential for improving data storage density and computing efficiency. Compared to the dual‐port memristor, greater attention should be paid to researching gate‐tunable memristor for image processing to improve the processing speed and reduce hardware resource consumption. Developing gate‐tunable memristor emulators is highly attractive given the immaturity of current fabrication of the gate‐tunable memristor. This work proposes a digital gate‐tunable memristor emulator based on Raspberry Pi, which addresses the non‐reconfigurability and inflexibility issues of the analog emulators. The proposed emulator can match the behavior of different memristor devices by regulating the gate voltage parameter. Additionally, it can operate at a maximum frequency of 500 MHz. To test the functionality of the proposed emulator, a digital implementation of the memristive circuit for motion detection is designed and verified experimentally. Experiments demonstrate that when moving object detection is performed on a 640 × 350 pixel video stream, low power consumption of 53 mW and a delay of 3.52 μs can be achieved.

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“…In the era of big data, the amount of data is growing explosively, and as a result, digital logic systems are having difficulty in processing such huge amounts of data while striving for ever-increasing efficiency [1]. To meet the demand of data processing speed and power efficiency, ternary logic has received recent attention due to its advantages of higher single-line information carrying capacity and additional logical functions [2][3][4][5][6][7]. Compared to the binary digital signal, each bit of the ternary digital signal contains more information, resulting in a higher transmission rate at the same frequency.…”

Section: Introductionmentioning

confidence: 99%

Design and Application of Memristive Balanced Ternary Univariate Logic Circuit

Wang,

Zhang,

Dong

et al. 2023

Micromachines

Self Cite

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This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.

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FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays

Cited by 9 publications

References 44 publications

Advances in pixel driving technology for micro-LED displays

Advances in pixel driving technology for micro-LED displays

A gate‐tunable memristor emulator for motion detection

Design and Application of Memristive Balanced Ternary Univariate Logic Circuit

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