FPGA resources reduction with multiplexing technique for implementation of ANN-based harmonics extraction by mp-q method

Abstract

An novel multiplexing technique applied on a neural harmonics extraction method is presented in this paper. This structure can be used in nonlinear loads compensation with Active Power Filters. The approach is composed of a neural Phase Lock-Loop and a neural reference current generator based on an efficient formulation of the instantaneous reactive power theory. For the purpose of harmonics suppression and reactive power compensation, the whole architecture is composed of three Adaline Neural Networks whose structure leads to an important consumption of Field Programmable Gate Array resources during implementation. The presented technique uses only one Adaline and keeps the immunity of the proposed approach under non-sinusoidal and unbalanced conditions of voltage. Simulation results of the neural harmonics detection system connected to a reference current control shows balanced and sinusoidal source currents under various conditions. Results with experimental measurement made on an Active Power Filters test bench demonstrate its good performances on harmonics filtering. Moreover, the simple structure from the new approach called mp-q method shows a significant resource reduction.Index Terms-FPGA, active power filters, instantaneous reactive power theory, power quality, resource reduction.

Neural harmonic detection approaches for FPGA area efficient implementation

“…an improved version of the three-monophase method [7] and another one called Two-Phase Flow introduced in [16]. In section III, those two approaches are compared to three other methods according to their modeling structure, their harmonic compensation performance and hardware resource consumption during implementation on a medium size FPGA target.…”