FPGA realization of multipurpose FIR filter

Reaz, Mamun Bin Ibne; Islam, Mohammad Tariqul; Sulaiman, M.S.; Ali, Mohd Alaudin Mohd; Sarwar, Hasan; Rafique, Shahida

doi:10.1109/pdcat.2003.1236448

Cited by 16 publications

(10 citation statements)

References 7 publications

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“…Such a regulator reduces the variations of voltage to a stable and acceptable level especially for product that are operated by portable battery such as cameras, hand phones, laptops. The study and research on power management techniques for different applications has been increasing rapidly for the last few years (Mohd-Yasin, Tan, & Reaz, 2004;Rosli, Mamun, Bhuiyan, & Husain, 2012;Chenchang & Hung, 2012;Peng, Changzhi, & Shuojie, 2012;Reaz et al, 2003;Nang, Ho, Jianping, & Or, 2011;Wu et al, 2011;Cheng, Yueh, & Liu, 2009;Akter, Reaz, Mohd-Yasin, & Choong, 2008) as a result of increased use of portable, handheld battery operated devices. Power management seeks to improve the power efficiency of devices resulting in prolonged battery life cycle and operating time for the device (Reaz, Choong, Sulaiman, & Mohd-Yasin, 2007;Akter, Reaz, Mohd-Yasin, & Choong, 2008;Romli, Mamun, Bhuiyan, & Hussain, 2012;Milliken, Martínez, & Sinencio, 2007;Kader, Rashid, Mamun, & Bhuiyan, 2012;Garimella & Furth, 2009;Marufuzzaman, Reaz, Rahman, & Ali, 2010;Arifin, Mamun, Bhuiyan, & Husain, 2012;Amin, Reaz, & Jalil, 2013;Reaz, Mohd-Yasin, Tan, Tan, & Ibrahimy, 2005).…”

Section: Introductionmentioning

confidence: 99%

A Low Drop-Out Voltage Regulator in 0.18 µm CMOS Technology

Bin

Aziz²,

Arif

et al. 2013

MAS

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Low Dropout regulators (LDOs) are essential devices for power supplies in almost all portable and hand-held electronic devices. The chip area of the usual LDO is still large and does not have the flexibility or adjustability of sampling resistor, output resistor and capacitors in error amplifier and series pass element. In this study, a Low Dropout regulator (LDO) circuit architecture with Mentor Graphic simulation software in 0.18 µm CMOS process technology with adjustable sampling resistor, output resistor and capacitors in error amplifier and series pass element is proposed. The proposed regulator design has the superiority that the sampling resistor, output resistor and capacitor is adjustable or can be changed when needed in error amplifier and series pass element. Moreover, the occupied chip area obtained is only (20.43 x 14.6) µm 2 .

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Section: Introductionmentioning

confidence: 99%

A Low Drop-Out Voltage Regulator in 0.18 µm CMOS Technology

Bin

Aziz²,

Arif

et al. 2013

MAS

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“…It comprises a wide variety of building blocks . Each block consists of programmable look-up table and storage registers, where interconnections among these blocks are programmed through the hardware description language [13]. This programmability and simplicity of FPGA made it favorable for prototyping digital system.…”

Section: Introductionmentioning

confidence: 99%

Hardware Approach of R-Peak Detection for the Measurement of Fetal and Maternal Heart Rates

Hasan

Mamun

2012

JART

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Fetal heart rate (FHR) monitoring is a routine for obtaining significant information about the fetal condition duringpregnancy and labour. Fetal condition may change abruptly during the pregnancy period. Therefore, a continuousfetal electrocardiogram (FECG) monitoring will ease the fetal well-being. An algorithm has been developed to detectR-peak for the simultaneous measurement of the fetal and maternal hearts rates during pregnancy and labor for fetalmonitoring. The algorithm is based on a cross-correlation, adaptive threshold and statistical properties in the timedomain. The performance achieved for the R-peak detection for the heart rate measurements shows that the modelcan extract R-peak for both, mother and fetus utilizing a single-lead configuration. The algorithm has beenimplemented in the field of propagation gate array (FPGA). The design was synthesized and fitted into Altera’s StratixEP1S10 using the Quartus II platform because of its enhanced DSP capability. Test case results showed an errorpercentage of around ±0.3% and ±0.5% for the R-peak detection of maternal and fetal mortality respectively. Thesystem is capable of running at a maximum clock frequency of 48.56MHz, and consumes 9633 logic elements,101616 memory space and 4 units of DSP blocks.

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“…It comprises a wide variety of building blocks. Each block consists of programmable look-up table and storage registers, where interconnections among these blocks are programmed through the hardware description language (Reaz et al, 2003;Amin et al, 2011). This programmability and simplicity of FPGA made it favorable for prototyping digital system.…”

Section: Introductionmentioning

confidence: 99%

Single Core Hardware Module to Implement Boolean Function Classification Techniques

Marufuzzaman

Mamun²,

Hashim³

et al. 2011

American Journal of Applied Sciences

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Problem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was performed by incorporating Boolean function classification into Huffman coding. This allows compression that was more efficient because the data had been categorized and simplified before the encoding was done. Simulation, timing analysis and circuit synthesis were commenced to verify the functionality and performance of the designated circuits which supports the practicality, advantages and effectiveness of the proposed single core hardware implementation. Results: The result shows a higher compression ratio. The average compression ratio was 25-37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz. Conclusion: The hardware implementation demonstrated complete, correct functionality and met all the initial system requirements.

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FPGA realization of multipurpose FIR filter

Cited by 16 publications

References 7 publications

A Low Drop-Out Voltage Regulator in 0.18 µm CMOS Technology

A Low Drop-Out Voltage Regulator in 0.18 µm CMOS Technology

Hardware Approach of R-Peak Detection for the Measurement of Fetal and Maternal Heart Rates

Single Core Hardware Module to Implement Boolean Function Classification Techniques

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