FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

Xie, Jiafeng; He, Jianjun; Tan, Guozhen

doi:10.1016/j.mejo.2010.04.006

Cited by 23 publications

(5 citation statements)

References 13 publications

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“…Other computer algorithms implemented in FPGAs described in this review includes CORDIC [1645][1646][1647], floating point [831,1648,1649], distributed arithmetic [1650,1651] and so on. Similarly, other implementations techniques for FPGAs found here were PWM [890,1652,1653], finite state machines [1654][1655][1656], scheduling [1657][1658][1659][1660], cellular automata [924,932], PLLs [950,1661,1662], ring oscillators [339, 962,1663], and so forth.…”

Section: Discussionmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Discussionmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…Similarly for power minimization, the corresponding objective function has been formulated by considering Hamming distance between filter coefficients. Power consumption in FIR filters can be minimized by reducing hardware complexity through filter implementation architecture (Arslan et al, 1996;Azarmehr and Ahmadi, 2012;Su et al, 1994;Mehendale et al, 1998;Hong et al, 2002;Xie et al, 2010) or by reducing switching activities between filter coefficients (Kavitha and Sasikumar, 2014;Najm, 1993;Nemani and Najm, 1996;Rahmeier et al, 2013;Shao et al, 2006) in their binary form, while processing through data buses of FPGA. In existing literature, Hamming distance (HD) between successive coefficients (Aktan et al, 2008;Gustafsson and Wanhammar, 2002;Mehendale et al, 1995;Merakos et al, 1997;Sankarayya et al, 1997) has been considered as a measure of switching activity.…”

Section: Introductionmentioning

confidence: 99%

Low power FIR filter design using modified multi-objective artificial bee colony algorithm

Dwivedi

Ghosh

Londhe

2016

Engineering Applications of Artificial Intelligence

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“…A popular design option is the Carry Save Adder (CSA) [4], where the carry propagation is accelerated at the expense of increasing the number of Full-Adder cells. While recent contributions to Dataflow Graph (DFG) transformation have optimized the use of CSAs [8][9][10][23][24], they also involve some drawbacks. For instance, in order to maximally reuse a CSA-tree, the cluster of operations that it implements must appear several times in different steps of the executed algorithm.…”

Section: Introductionmentioning

confidence: 99%

Improving circuit performance with multispeculative additive trees in high-level synthesis

Barrio¹,

Hermida²,

Memik³

et al. 2014

Microelectronics Journal

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Abstract-The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space of High-LevelSynthesis (HLS). Nevertheless their use is restricted to only few operators in the datapaths because the number of cases to control grows exponentially. In this work an instance of VLFUs is described, and based on its structure, the average latency of tree structures is improved. Multispeculative Functional Units (MSFUs) are arithmetic Functional Units that operate using several predictors for the carry signal. In spite of utilizing more than a predictor, none or only one additional very short cycle is enough for producing the correct result in the majority of the cases. In this paper our proposal takes advantage of multispeculation in order to increase the performance of tree structures with a negligible area penalty. By judiciously introducing these structures into computation trees, it will only be necessary to predict the carry signals in certain selected nodes, thus minimizing the total number of predictions and the number of operations that can potentially mispredict. Hence, the average latency will be diminished and thus performance will be increased. Our experiments show that it is possible to improve 26% execution time. Furthermore, our flow outperforms previous approaches with Speculative FUs.

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FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

Cited by 23 publications

References 13 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

Low power FIR filter design using modified multi-objective artificial bee colony algorithm

Improving circuit performance with multispeculative additive trees in high-level synthesis

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