FPGA realization of a split radix FFT processor

Abstract

Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to choose the algorithm and architecture to implement it. This paper explains the realization of a Split Radix FFT (SRFFT) processor based on a pipeline architecture reported before by the same authors. This architecture has as basic building blocks a Complex Butterfly and a Delay Commutator. The main advantages of this architecture are:• To combine the higher parallelism of the 4r-FFTs and the possibility of processing sequences having length of any power of two.• The simultaneous operation of multipliers and adder-subtracters implicit in the SRFFT, which leads to faster operation at the same degree of pipeline. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaining high performance at economical price and a short time of realization. The Delay Commutator has been designed to be customized for even and odd SRFFT computation levels. It can be used with segmented arithmetic of any level of pipeline in order to speed up the operating frequency. The processor has been simulated up to 350 MHz, with an EP2S15F672C3 Altera Stratix II as a target device, for a transform length of 256 complex points.

Fuzzy optimization FFT circuit for image processing

“…After analyzing the radix-4 FFT algorithm, this project advanced a 64-point FFT processor implementation, which has many advantages. 1,2 This paper studies the content as follows: first, describe the FFT algorithm. Then, introduce the principle of FPGA architecture, performance and characteristics, combined with the theory of FFT algorithms to determine the FPGA devices as a FFT algorithm basis.…”

Design of DPX system for real-time spectrum analysis and signal detection

“…The FPGA1 also includes an external 4-access fiber interface to exchange data with other devices. The FPGA2 is also connected with a 2GByte DDR2 memory, and at the same time a large capacity CF card and a FLASH are connected to FPGA2 via System ACE controller [7,8,12]. The high-speed sampling clock is generated by the board.…”

“…It is well suited for application in the realtime spectrum analysis and signal detection, and has found an increasingly wide utilization in many fields such as electronic reconnaissance and disturber diagnosis [4,5,6]. To apply the DPX, the process of generating the DPX images is analyzed and a practical DPX system is designed and implemented referring other electron systems [7,8,9,10,11,12]. Fig.…”

“…The main data processing unit employs dual-FPGA architecture [8]. The input analog signal is digitized by the A/D converter (AT84AS003, 3 GHz analog input bandwidth, 1.5 GHz sampling rate maximum, 10-bit), the digital signal is sent to FPGA1 (XC5VSX95T, 14,720 slices, 8,784 kb BRAM, 640 IO) to calculate the frequency waveform applying the FFT arithmetic [9,10,11,12], and the result is transmitted to FPGA2 (XC4VFX100, 42,176 slices, 6,768 kb BRAM, 2 embedded PowerPC processor cores, 768 IO) for the accumulation of the 3-D spectrum. The two FPGAs are interconnected through a self-defined bus.…”