FPGA realization of a speech encryption system based on a generalized modified chaotic transition map and bit permutation

Sayed, Wafaa S.; Tolba, Mohamed F.; Radwan, Ahmed G.; Abd-El-Hafiz, Salwa K.

doi:10.1007/s11042-018-6946-9

Cited by 26 publications

(9 citation statements)

References 44 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As can be seen, all these results are more uniform and different than the original speech file and have no similarity to the input speech signal. [53]. The correlation coefficients should be close to zero and the entropy close to the ideal value of 16 bits/sample.…”

Section: Encryption Performance Analysismentioning

confidence: 97%

DS2B: Dynamic and Secure Substitution Box for Efficient Speech Encryption Engine

et al. 2021

Self Cite

View full text Add to dashboard Cite

This paper proposes an efficient encryption technique based on Dynamic and Secure Substitution Box (DS2B) design suitable for IoT and resource-constrained platforms. The DS2B has the advantages of simple structure and good encryption performance. A different number of strong S-boxes could be generated with minor variations in the DS2B parameters. Performance analyses of the DS2B, including differential/linear cryptanalysis, bijective, nonlinearity, strict avalanche criterion (SAC), and bit independence criterion (BIC) have been presented where high nonlinearity, and low differential uniformity are achieved. Besides, a comparison with recent S-boxes is introduced which shows the robustness of the DS2B. To verify the DS2B, a speech encryption engine was realized on FPGA. Various security analyses were evaluated including the National Institute of Standards & Technology (NIST) statistical test suite, number of samples changes rate NSCR, mean square error (MSE), correlation, histogram, and spectrogram. In this work, the silence periods are encrypted in a way that makes them much harder to detect using the DS2B. The proposed encryption scheme achieved a throughput of 9.87 G bit/s, which is higher than previous work. A Xilinx Nexys 4 FPGA evaluation board was used for implementing and verifying the design.

show abstract

Section: Encryption Performance Analysismentioning

confidence: 97%

DS2B: Dynamic and Secure Substitution Box for Efficient Speech Encryption Engine

et al. 2021

Self Cite

View full text Add to dashboard Cite

show abstract

“…This generic FPGA system can realize many fractional-order applications on hardware, e.g., edge detection [38], [39], control [40], [41], synchronization [42] and encryption [43]. Additionally, it can replace the current realizations of mixed-signal and digitally implemented fractional-order applications with the reconfigurable one, e.g., analog/mixed-signal systems [44], [45], control [46] and encryption [12], [47]- [49]. Furthermore, it can be used in variable-order chaotic systems [50], [51], dynamic switching and synchronization [52], and encryption applications with dynamic encryption key [53].…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable FPGA Realization of Fractional-Order Chaotic Systems

et al. 2021

Self Cite

View full text Add to dashboard Cite

This paper proposes FPGA realization of an IP core for generic fractional-order derivative based on Grünwald-Letnikov approximation. This generic design is applied to achieve reconfigurable realization of fractional-order chaotic systems. The fractional-order real-time configuration boosts the suitability of this particular realization for different applications, including dynamic switching, synchronization, and encryption. The proposed design targets optimized utilization of the FPGA internal resources and efficient employment of the external peripherals: switches and I/O ports in the FPGA board. The digital design of the fractional-order dependent terms: binomial coefficients and power function is proposed. Three approximations of the power function using curve fitting are compared, settling on the quadratic approximation that balances accuracy and efficiency. Three fractional-order chaotic systems: Liu, Li and Chen four-wing, are verified for both commensurate and incommensurate orders cases, using one approach for the commensurate order case and two approaches for the incommensurate order case. The reconfigurable design is realized on the Artix-7 FPGA board, yielding throughputs of 1.1266, 1.1266, and 1.434 Gbit/s for both commensurate and incommensurate orders cases of the three systems, respectively. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

show abstract

“…Consequently, it is hot for researchers to focus on the image and video data encryption, where the encrypted sequences are generated by chaotic systems in order to satisfy the need for remote communications and other applications. Multiple hardware platforms are implemented on encryptions such as FPGA, ARM, or circuits implementation [19][20][21][22][23][24][25][26][27][28][29][30][31][32].…”

Section: Introductionmentioning

confidence: 99%

“…e study in [26] implements the multibutterfly chaotic attractor problem on FPGA. e study in [27] proposes a Kolmogorov-type three-dimensional chaotic system and implements the chaotic system on FPGA. e study in [28] implements an application of highdimensional digital chaos system (HDDCS) in image encryption in a limited precision range on FPGA.…”

Section: Introductionmentioning

confidence: 99%

Analyses and Encryption Implementation of a New Chaotic System Based on Semitensor Product

Wang

Zhong

et al. 2020

Complexity

View full text Add to dashboard Cite

Semitensor product theory can deal with matrices multiplication with different numbers of columns and rows. Therefore, a new chaotic system for different high dimensions can be created by employing a semitensor product of chaotic systems with different dimensions, so that more channels can be selected for encryption. This paper proposes a new chaotic system generated by semitensor product applied on Qi and Lorenz systems. The corresponding dynamic characteristics of the new system are discussed in this paper to verify the existences of different attractors. The detailed algorithms are illustrated in this paper. The FPGA hardware encryption implementations are also elaborated and conducted. Correspondingly, the randomness tests are realized as well, and compared to that of the individual Qi system and Lorenz system, the proposed system in this paper owns the better randomness characteristic. The statistical analyses and differential and correlation analyses are also discussed.

show abstract

FPGA realization of a speech encryption system based on a generalized modified chaotic transition map and bit permutation

Cited by 26 publications

References 44 publications

DS2B: Dynamic and Secure Substitution Box for Efficient Speech Encryption Engine

DS2B: Dynamic and Secure Substitution Box for Efficient Speech Encryption Engine

Reconfigurable FPGA Realization of Fractional-Order Chaotic Systems

Analyses and Encryption Implementation of a New Chaotic System Based on Semitensor Product

Contact Info

Product

Resources

About