FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

Abstract

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

Low Power QC-LDPC Decoder Based on Token Ring Architecture

“…Nevertheless, an attempt was made to compare the proposed Token Ring-based architecture for the WiGig standard code. This is presented in Table 6, where NMS means Normalized Min-Sum decoder algorithm, which is a slightly modified decoding computation method in control nodes of the presented Min-Sum algorithm [37]. The design proposed in this article will be recommended in the systems when the maximum possible throughput is not critical, while maintaining a reduced P d value, which has a direct impact on the temperature generated in the integrated circuit.…”

“…In BP, beliefs are propagated between nodes in a Tanner graph [36] representation of an LDPC code. This graph is a bipartite graph with so-called control nodes representing rows of H, bit nodes representing columns of H and edges representing nonzero positions in H. The commonly used simplified method for determining the beliefs (messages propagated between nodes in the algorithm) is known as the Min-Sum algorithm [37][38][39]. The decoding process is an estimation process of the transmitted code vector M(n)-a set of row indexes in the parity check matrix H containing one in the n-th column, R mn -message from the m-th control vertex to the n-th bit vertex of Tanner graph, X n -the n-th value of the decoded vector.…”

“…This processing scheme allows for significant reduction of the energy consumption due to activating the clock signal delivered to computation logic only in the needed time slot. Table 1 presents the analysis of the operating time of individual decoder elements and the number of Adaptive Logic Module (ALM) blocks [37,42] utilized by the designed QC-LDPC implementation. These results have been obtained for a single-iteration-decoding of a QC-LDPC regular matrix with dimensions 512 × 1024 (M × N), P = 64 and Z = 3072, where Z is the number of nonzero elements of the parity check matrix H. During normal operation, in the first iteration the decoder performs initialization once and in the last iteration it communicates the results module.…”

FPGA based Industrial Ethernet Network Analyser for Real-time Systems Providing Openness for Industry 4.0

“…FPGA may be applied in many areas requiring fast data processing, for example, data security (Opara, Kubica, and Kania 2019) or real-time processing (Hayajneh et al 2017). There also exist implementations of the FPGA in a range of devices dedicated for Ethernet traffic monitoring, for example, Livetap based on Spartan 6 FPGA (Kuc, Sułek, and Kania 2020). Solutions of this type are implemented with the use of more complex systems, equipped with four Ethernet ports 1 Gb or 10Gb and PCI or PCIe interface, such as NetFPGA (Jyothi et al 2016).…”