FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers

Abstract

Abstract-FPGA-optimised Random Number Generators (RNGs) are more resource efficient than software-optimised RNGs, as they can take advantage of bit-wise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimised RNGs, so they are not commonly used in real-world designs. This paper describes a new type of FPGA RNG called a LUT-SR RNG, which takes advantage of bit-wise XOR operations and the ability to turn LUTs into shift-registers of varying lengths. This provides a good resource-quality balance compared to previous FPGA-optimised generators, between the previous high-resource high-quality LUT-FIFO RNGs and lowresource low-quality LUT-OPT RNGs. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within the paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in the paper, backed up by an online set of VHDL generators and test-benches.

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures

“…As n exceeds 32, the number of possible primitive polynomials increases greatly, but the number in the candidate set slowly decreases. 4 However, the rate of decline is slow enough so that there are plenty of candidates in the set: when n = 10 3 , there are over a million primitive candidates, and when n = 10 4 , there are still hundreds of thousands.…”

“…The LUT-SR family was first presented in a conference paper [4], which concentrated on the practical aspects of constructing and using these generators. This paper adds Section V, which describes the method used to find maximum period generators, Section VI, which describes the process used to select the highest quality generators, and Section VIII, which gives a rigorous theoretical quality analysis in terms of equidistribution.…”

High Quality FPGA Optimized Random Number Generator

“…The new The new RNGs introduced here are part of a large family of RNGs, all of which are based on binary linear recurrences. This family includes many of the most popular contemporary software generators, such as the Mersenne Twister (MT19937) [4], the Combined Tausworthe (Taus113) [11], and TT800 [5]. Many of these software generators have been adapted for use in FPGAs [6]- [8], but the convenience of mapping an algorithm designed for word-level software comes at the cost of reduced efficiency, flexibility and low precision.…”

Real-time Foreground Object Detection Combining the PBAS Background Modelling Algorithm and Feedback from Scene Analysis Module

“…Three colour channels are split and directed to three separate instances of the processing unit. Pseudo-random number generation is carried out using the concept described in [21]. It is worth noting that the authors of paper [21] made the VHDL code of different RNG versions available.…”

“…Pseudo-random number generation is carried out using the concept described in [21]. It is worth noting that the authors of paper [21] made the VHDL code of different RNG versions available. This allows a quick integration of the module with the whole system.…”