FPGA-NHAP: A General FPGA-Based Neuromorphic Hardware Acceleration Platform With High Speed and Low Power

Liu, Yijun; Chen, Yuehai; Ye, Wujian; Gui, Yu

doi:10.1109/tcsi.2022.3160693

Cited by 24 publications

(9 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In these systems, neurons only run when there are spikes at its input, which can help achieve better efficiencies. In recent years, some clock-driven FPGA implementations have been proposed, which extensively use parallelization in large FPGA devices to obtain high speeds in relatively low area and power [22,23].…”

Section: Motivation and Previous Workmentioning

confidence: 99%

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

López-Asunción,

Ituero

2024

Electronics

View full text Add to dashboard Cite

Spiking neural networks (SNNs) promise to perform tasks currently performed by classical artificial neural networks (ANNs) faster, in smaller footprints, and using less energy. Neuromorphic processors are set out to revolutionize computing at a large scale, but the move to edge-computing applications calls for finely-tuned custom implementations to keep pushing towards more efficient systems. To that end, we examined the architectural design space for executing spiking neuron models on FPGA platforms, focusing on achieving ultra-low area and power consumption. This work presents an efficient clock-driven spiking neuron architecture used for the implementation of both fully-connected cores and 2D convolutional cores, which rely on deep pipelines for synaptic processing and distributed memory for weight and neuron states. With them, we developed an accelerator for an SNN version of the LeNet-5 network trained on the MNIST dataset. At around 5.5 slices/neuron and only 348 mW, it is able to use 33% less area and four times less power per neuron as current state-of-the-art implementations while keeping low simulation step times.

show abstract

Section: Motivation and Previous Workmentioning

confidence: 99%

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

López-Asunción,

Ituero

2024

Electronics

View full text Add to dashboard Cite

show abstract

“…As one of the most extensively adopted reconfigurable architectures, field programmable gate array (FPGA) with matrix of configurable logic blocks and complex interconnection routing to be customed on demand, has been broadly used as accelerator board for neuromorphic hardware owing to the flexibility of semi-customized characteristics. [88,97,[298][299][300] Reconfigurability of FPGA mostly stems from reprogrammable routing architecture which consumes ≈ 90% of the FPGA resources. Meanwhile, look-up tables, the key functional component of configurable logic blocks, can be fully assembled to realize programmable logic functions, which also contribute to FPGA's reconfigurability.…”

Section: Neuromorphic Integration Implemented With Cmos-based Devicesmentioning

confidence: 99%

“…Apart from mature FPGA-inspired neuromorphic platforms that mimic biological neural networks from the functional perspective, [298][299][300] another important thread is to structurally approximate the biological functional components from the fundamental device perspective which highlights a more biomimetic approach. [13,89] Individual neuron with various behavior functions can be independently reconfigured with a time-multiplexed circuit and each synaptic weight can be flexibly modulated, which make for successful implementation of device-level reconfigurability.…”

Section: Neuromorphic Integration Implemented With Cmos-based Devicesmentioning

confidence: 99%

Reconfigurable Neuromorphic Computing: Materials, Devices, and Integration

Chen

Guo

et al. 2023

Advanced Materials

View full text Add to dashboard Cite

Neuromorphic computing has been attracting ever‐increasing attention due to superior energy efficiency, with great promise to promote the next wave of artificial general intelligence in the post‐Moore era. Current approaches are, however, broadly designed for stationary and unitary assignments, thus encountering reluctant interconnections, power consumption, and data‐intensive computing in that domain. Reconfigurable neuromorphic computing, an on‐demand paradigm inspired by the inherent programmability of brain, can maximally reallocate finite resources to perform the proliferation of reproducibly brain‐inspired functions, highlighting a disruptive framework for bridging the gap between different primitives. Although relevant research has flourished in diverse materials and devices with novel mechanisms and architectures, a precise overview remains blank and urgently desirable. Herein, the recent strides along this pursuit are systematically reviewed from material, device, and integration perspectives. At the material and device level, we comprehensively conclude the dominant mechanisms for reconfigurability, categorized into ion migration, carrier migration, phase transition, spintronics, and photonics. Integration‐level developments for reconfigurable neuromorphic computing are also exhibited. Finally, a perspective on the future challenges for reconfigurable neuromorphic computing is discussed, definitely expanding its horizon for scientific communities.This article is protected by copyright. All rights reserved

show abstract

“…20 With the advances in SNNs hardware platforms, SNNs implemented on neuromorphic hardware provide efficient and low-latency solution in event-based vision, especially in some resource-constrained real-world applications, such as target recognition, autonomous driving, and robot control. [21][22][23][24][25] SNNs with various learning rules have been applied in event stream tasks. Zhao et al 26 used SNN with Tempotron learning rule in event streams classification.…”

Section: Introductionmentioning

confidence: 99%

Event camera object recognition using spatiotemporal event time surface and reward-modulated spike-timing-dependent plasticity learning rule

Zhou,

Zhang

2024

J. Electron. Imag.

View full text Add to dashboard Cite

Event cameras record moving objects with asynchronous event streams. It remains a challenge to make full use of the spatiotemporal information of event streams to extract high-quality features and to make event camera object recognition. We propose an event-based event camera object recognition system, which includes a denoising module and an object recognition module. The denoising module removes noise events using spatiotemporal information of the events. The object recognition module extracts primary spatiotemporal features based on the event time surface prototypes obtained by clustering, then further extracts complex diagnostic features, and makes object recognition using spiking neural networks with reward-modulated spike-timing-dependent plasticity learning rule. Experimental results demonstrate that our system has better performance than baseline methods on five popular event camera datasets, especially on datasets with rich spatiotemporal dynamics. Our denoising method improves the noise robustness of our event camera object recognition system on high-speed moving datasets that are greatly affected by noises. Moreover, our method has much better recognition ability than baseline methods when using short input event streams. Our method is very beneficial for developing event-based event camera object recognition algorithm when event streams are short or noises are serious.

show abstract

FPGA-NHAP: A General FPGA-Based Neuromorphic Hardware Acceleration Platform With High Speed and Low Power

Cited by 24 publications

References 22 publications

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

Reconfigurable Neuromorphic Computing: Materials, Devices, and Integration

Event camera object recognition using spatiotemporal event time surface and reward-modulated spike-timing-dependent plasticity learning rule

Contact Info

Product

Resources

About