FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

Abstract

This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular, we use the large embedded memories available in the Xilinx Virtex-II pro FPGAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec.

Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks

“…Nonetheless, if S is a non-linear operation, this equality does not hold, and it is necessary to use judiciously both shares to be able to compute S(z). This operation is costly in general [26] (unless some algebraic properties of the non-linear function S can be taken advantage of [19]) and error-prone [13].…”

Entropy-based power attack

“…The internal variable x does not exist as a net in the cryptosystem but can be reconstructed by a pair of signals (m, x m = x θ m) where x m is the masked variable and θ is an operation which can be Boolean or arithmetic. In the sequel, we consider the masked DES studied at UCL [21]; our variable x represents the right half of the LR register.…”

Evaluation of countermeasure implementations based on Boolean masking to thwart side-channel attacks

“…A solution in hardware consists in using a two-path implementation, one for the masked variable and one for the mask itself, as proposed in [13] on a Data Encryption Standard (DES) example illustrated in Fig. 1.…”