FPGA Implementations of Layered MinSum LDPC Decoders Using RCQ Message Passing

Abstract

Non-uniform message quantization techniques such as reconstruction-computation-quantization (RCQ) improve error-correction performance and decrease hardware complexity of low-density parity-check (LDPC) decoders that use a flooding schedule. Layered MinSum RCQ (L-msRCQ) enables message quantization to be utilized for layered decoders and irregular LDPC codes. We investigate field-programmable gate array (FPGA) implementations of L-msRCQ decoders. Three design methods for message quantization are presented, which we name the Lookup, Broadcast, and Dribble methods. The decoding performance and hardware complexity of these schemes are compared to a layered offset MinSum (OMS) decoder. Simulation results on a (16384, 8192) protograph-based raptor-like (PBRL) LDPC code show that a 4-bit L-msRCQ decoder using the Broadcast method can achieve a 0.03 dB improvement in errorcorrection performance while using 12% fewer registers than the OMS decoder. A Broadcast-based 3-bit L-msRCQ decoder uses 15% fewer lookup tables, 18% fewer registers, and 13% fewer routed nets than the OMS decoder, but results in a 0.09 dB loss in performance.

A Reconstruction-Computation-Quantization (RCQ) Approach to Node Operations in LDPC Decoding

“…thermometer-to binary decoder We have implemented all three of these methods and explored their performance and resource utilization in [2].…”

“…Each design meets timing with a 500 MHz clock. The broadcast method described in [2] is used for RCQ design. Table I summarizes the hardware usage of each decoder.…”

“…Fig. (b) shows the proposed L-msRCQ decoder in[2], which features separate RCQ parameters for each layer.…”