FPGA implementation of the MMRRS scheduling algorithm for VOQ switches

Simulation and FPGA-Based Implementation of Iterative Parallel Schedulers for Optical Interconnection Networks

“…On the other hand, the iterative implementation of LQF (i.e., iLQF) is known to outperform iSLIP to the detriment of a larger number of iterations required for convergence, i.e., N instead of log N, where N is the number of ports [14]. Other scheduling algorithms have been proposed such as maximal matching with round-robin selection, which outperforms iSLIP at high loads (greater than 70%) [15], and the parallel hierarchical matching schedulers [16], which outperform iSLIP for low numbers of iterations [16]. Yet among the various schedulers, iSLIP stands out for its low complexity and performance [17], whereas the delay improvement of longest-queue-first approaches is still valuable, for instance, in two-step schedulers [5].…”

“…iSLIP hardware implementation has been shown to outperform two other schedulers (namely lonely output [19] and wavefront allocator [20]) [21]. Other hardware implementations targeted other maximal matching algorithms, such as noniterative maximal matching with round-robin selection [15] and the sequential non-iterative matching algorithm [22]. A hardware implementation of the iSLIP algorithm modified for supporting the blocking behavior of the architecture used for the photonic integrated interconnection network is presented in [23].…”