FPGA implementation of the MIMO-OFDM physical layer using single FFT multiplexing

Park, Jeoong Sung; Ogunfunmi, Tokunbo

doi:10.1109/iscas.2010.5537043

Cited by 9 publications

(7 citation statements)

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“…For example, 20 MHz sampling in our system means one data item is sampled among five input data on 100 MHz system frequency. That type of data sampling is to avoid clock domain crossing problem [19].…”

Section: Pipelined Architecture For Mimo-ofdmmentioning

confidence: 99%

“…Different from the previous three stage pipelined architecture in [17] and [19], our new pipelined architecture consists of four stages as presented in Fig. 6.…”

Section: Hardware Implementationmentioning

confidence: 99%

“…It uses single radix-4 FFT block that is shared across modulations for MIMO-OFDM system. In [19], we extend the number of channels up to 3 × 3 MIMO-OFDM system to show efficiency and scalability of our pipelined architecture.…”

mentioning

confidence: 99%

“…Our previous systems in [17] and [19] simply parse one channel into multiple channels by using the TDM parser since they assume an ideal channel without any noise and distortion. However, TDM is not useful when each channel is overlapped.…”

mentioning

confidence: 99%

“…The TDM parser (deparser) is replaced with the Alamouti encoder (decoder) to make the system helpful for working on a real channel. Besides, one more stage for Alamouti encoding is added onto the three stage pipelined architecture in [17] and [19].…”

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confidence: 99%

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Efficient FPGA-Based Implementations of MIMO-OFDM Physical Layer

Park

Ogunfunmi

2012

Circuits Syst Signal Process

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Recently, Multiple-input Multiple-output and Orthogonal Frequency Division Multiplexing (MIMO-OFDM)-based technologies have been deployed in advanced wireless communication systems. In this paper, we present a prototype Field Programmable Gate Array (FPGA) design for an efficient physical layer implementation of a MIMO-OFDM technique. We propose a pipelined architecture using a Fast Fourier Transform that is shared across modulations for the MIMO-OFDM system. As more channels are used, more resources can be saved by using our proposed architecture. Experimental results show that the proposed implementation saves at least 40 percent of the hardware resources, while achieving the same data rate as known baseline MIMO-OFDM implementations. In addition, we propose efficient hardware implementation of the Almouti encoder and decoder. They are also designed to use minimum hardware resource by using the proposed architecture.

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Section: Pipelined Architecture For Mimo-ofdmmentioning

confidence: 99%

“…Different from the previous three stage pipelined architecture in [17] and [19], our new pipelined architecture consists of four stages as presented in Fig. 6.…”

Section: Hardware Implementationmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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