FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique

Datta, Debarshi; Akhtar, Sahil; Dutta, Himadri Sekhar

doi:10.1109/vlsidcs47293.2020.9179926

Cited by 5 publications

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“…Therefore, it is advisable to calculate the filter coefficients in advance and store them in the device memory. Moreover, when the form of the filter coefficients is known in advance, this allows to optimize device architecture [15].…”

Section: Introductionmentioning

confidence: 99%

Digital Filter Architecture Based on Modified Winograd Method F(2× 2, 5× 5) and Residue Number System

et al. 2023

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Improving the characteristics of digital signal processing devices is an important task in many practical problems. The paper proposes the architecture of a two-dimensional digital filter with a 5 × 5 mask, in which calculations are performed according to the Winograd method in the Residue Number System (RNS) with moduli of a special type. Theoretical analysis and hardware Field-Programmable Gate Array simulation are presented. The results show that the fragment throughput fr/s (number of fragments per second) of the device is 29.6% -724.7% higher than state-of-the-art solutions. This is achieved by the combination of the Winograd method, which reduces the number of multiplications, with the RNS arithmetic, which performs addition and multiplication under smaller operands in parallel. However, our experiments showed that the proposed method requires up to 2.54% -11.01% more Look-Up Tables and 3.58% -19.83% higher power consumption compared to known analogues.

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Section: Introductionmentioning

confidence: 99%