FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time

Hazra, Sambaran; Ghosh, Sudip; De, Sayandip; Rahaman, Hafizur

doi:10.1007/s11554-017-0672-9

Cited by 14 publications

(4 citation statements)

References 28 publications

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“…Compared with [29] in terms of throughput per Watt, our design is three orders of magnitude faster, which is consistent with the FPGA implementation results. In conclusion, the power consumption of the proposed design is lower than in most recent works, such as [29,36,37], due to the eliminations of the DCT and IDCT, and the 5/6 of the computational cost saved in color space conversion. Due to the low computational cost, parallel computing and a pipeline strategy (unlike [29], one divider is shared in all modules) can be used with the proposed method to improve the throughput of our design, which contributes to the high power efficiency.…”

Section: Hardware Implementation Comparisonmentioning

confidence: 81%

A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

et al. 2021

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This paper presents an invisible and robust watermarking method and its hardware implementation. The proposed architecture is based on the discrete cosine transform (DCT) algorithm. Novel techniques are applied as well to reduce the computational cost of DCT and color space conversion to achieve low-cost and high-speed performance. Besides, a watermark embedder and a blind extractor are implemented in the same circuit using a resource-sharing method. Our approach is compatible with various watermarking embedding ratios, such as 1/16 and 1/64, with a PSNR of over 45 and the NC value of 1. After Joint Photographic Experts Group (JPEG) compression with a quality factor (QF) of 50, our method can achieve an NC value of 0.99. Results from a design compiler (DC) with TSMC-90 nm CMOS technology show that our design can achieve the frequency of 2.32 GHz with the area consumption of 304,980.08 μm2 and power consumption of 508.1835 mW. For the FPGA implementation, our method achieved a frequency of 421.94 MHz. Compared with the state-of-the-art works, our design improved the frequency by 4.26 times, saved 90.2% on area and increased the power efficiency by more than 1000 fold.

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Section: Hardware Implementation Comparisonmentioning

confidence: 81%

A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

et al. 2021

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“…It is noticeable that their method only concentrates on small size and gray scaler image with 64 × 64. Although our method only achieves the second best performance next to [51], ours can afford a more powerful ability of processing color image with larger size. Concretely, the data processing capacity is 468.75 ( 3 × (800 × 800)/(64 × 64) ) times of theirs.…”

Section: E Comparisons With State-of-the-artsmentioning

confidence: 92%

“…Table 7 shows the comparison results between these proposed methods. According to Table 7, [51] achieved the maximum on the Max Frequency metric of the whole watermarking system, which means that they method would cost a lowest operating latency to process single. It is noticeable that their method only concentrates on small size and gray scaler image with 64 × 64.…”

Section: E Comparisons With State-of-the-artsmentioning

confidence: 99%

A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

2020

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Digital watermarking has the properties such as invisibility and anti-aggression, so the digital watermarking technology has been widely used in copyright protection, information hiding. The watermarking technology takes into account the invisibility and robustness of the watermark by controlling the embedding intensity and position of the watermark mainly in the transformation domain. In this paper, discrete cosine transform (DCT) is adopted to transform the given image from spatial domain to frequency domain for adding watermark information. In order to meet the demands of image watermarking batch processing and cloud processing in the future, this paper optimized the DCT algorithm and the data precision, and successfully deployed the designed accelerator kernel on the FPGA cloud platform to speed up the processing of watermarking. The implementation of data processing based on cloud platform is the development trend of big data era. The cloud platform adopted in this paper is based on the OpenCL heterogeneous architecture combining CPU and FPGA. The cloud-based implementation makes digital watermarking application highly extensible, widely shareable, and more secure. The whole system implements a series of complete cloud processes including image decoding, image preprocessing, watermark embedding, and watermarked image encoding. The watermarking algorithm is accelerated by the efficient parallel computing capabilities of FPGA. It can be seen that the result of acceleration is remarkable, providing the state-of-the-art throughput of 1.676 GBps and the highest processing speed of 937 FPS for 800 × 800 sized colorimage. INDEX TERMS Cloud services, parallel operation, integer DCT, data encryption and watermarking, heterogeneous architecture.

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“…In the last paper of the third theme entitled ''FPGA Implementation of Semi-Fragile Reversible Watermark by Histogram Bin Shifting for Real-Time'' by Hazra et al [17], field programmable gate array (FPGA) implementation of reversible watermarking (RW) algorithm based on histogram bin shifting (HBS) that can be used for real-time applications of medical and military images has been presented. The embedding and extracting procedures involved in the proposed scheme are implemented using Xilinx system generator.…”

Section: Real-time Data Hiding and Visual Cryptographymentioning

confidence: 99%