FPGA Implementation of Reconfigurable FIR Filter using Carry Bypass Adder

Abstract

Software-Defined Radio (SDR) is a radio communication system where components that have been traditionally implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented by means of software on a personal computer or embedded system. Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in SDR systems, whose filter co-efficient change dynamically during runtime. In this paper, Low Cost Carry Bypass adder Reconfigurable Finite Impulse Response (LC-CBA-RFIR) is introduced to perform the RFIR filter operations. DRAM-based Reconfigurable Partial Product Generators (DRPPG) consists of MUX and dual port distributed RAM, which has co-efficient to perform a FIR filter operation. With the help of Verilog code, the RFIR filter architecture was verified in Modelsim software. The same Verilog code was used to analyse the FPGA performances such as LUT, flip flop, slice and frequency. After implementing FPGA, all the performance improved in LC-CBA-RFIR method compared to the conventional methods.