2013 IEEE Student Conference on Research and Developement 2013
DOI: 10.1109/scored.2013.7002592
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FPGA implementation of RANSAC algorithm for real-time image geometry estimation

Abstract: Random Sample Consensus (RANSAC) is commonly used in many estimation tasks especially in computer vision applications due to its simplicity. This paper presents a hardware/software co-design implementation of RANSAC algorithm for real-time affine geometry estimation on a field programmable gate array (FPGA) platform. Double buffering technique is used to store and process data in pipeline. Experimental result shows that the proposed system managed to speed up the software process by about 11.4 times for 100 da… Show more

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Cited by 9 publications
(5 citation statements)
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“…RANSAC has been implemented in FPGAs. In [ 120 ], an implementation for real-time affine geometry estimation is introduced. The main task chosen to be accelerated was the fitness scoring function, where the authors claim that the speed-up factor increases with input data size.…”
Section: Applicationsmentioning
confidence: 99%
“…RANSAC has been implemented in FPGAs. In [ 120 ], an implementation for real-time affine geometry estimation is introduced. The main task chosen to be accelerated was the fitness scoring function, where the authors claim that the speed-up factor increases with input data size.…”
Section: Applicationsmentioning
confidence: 99%
“…A hardware architecture and organization of the RANSAC for feature-based image registration are proposed in [20]. Additionally, a hardware/software co-design platform of RANSAC algorithm for real-time affine geometry estimation is presented in [21]. The most intensive computation, i.e.…”
Section: Hardware Accelerated Ransac Approachesmentioning
confidence: 99%
“…RANSAC is an iterative algorithm to find the affine model that best describes the transformation of the two subsequent frames. Unlike the conventional RANSAC [38], this work uses an upper bound time to terminate RANSAC computation (similar to [39]) regardless of the number of iterations due to the real-time constraint as illustrated in Algorithm 1.…”
Section: Ransacmentioning
confidence: 99%
“…Accelerator. RANSAC hardware design in [39] is utilized in this work, which accelerates only fitness scoring step. As described in Algorithm 2, fitness scoring is an iterative process which performs similar computation to all data samples based on hypothesis model.…”
Section: Ransac Hardwarementioning
confidence: 99%