FPGA implementation of MMSE channel estimation algorithm using system generator

Sanli, Mahir; Öztürk, Mustafa; Balcisoy, Ersen; Karakoc, Murat Can; Kirkaya, Emre; Çıçek, Adem; Özyurt, Serdar; Cavus, Enver

doi:10.1109/siu.2018.8404706

Cited by 1 publication

(2 citation statements)

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“…It can be seen from the DMRS structure of Figure 2 that for each subcarrier, only two users send the DMRS, and the other two users do not send data. Taking DMRS ports 0 and 1 as an example, user 3 and user 4 do not send data that the corresponding s 3 and s 4 are both 0, so Equation ( 1) can be simplified to Equation (2).…”

Section: Channel Estimation At Pilotmentioning

confidence: 99%

“…The fifth generation mobile communication technology, 5G, has higher speed, lower delay and denser connections than 4G. With the gradual development of commercial deployment of 5G networks, 5G small cells built to supplement the radiation blind area of the macrocell [1][2][3] are becoming more popular. In the macrostation, it is a common practice to use an application-specific integrated circuit (ASIC) as the solution for the base station hardware module.…”

Section: Introductionmentioning

confidence: 99%

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An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells

Long

Liu

Sun

2022

Sensors

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As 5G small cells gradually become the main force of 5G indoor deployment, it is necessary to study channel estimators for 5G small base stations, but there has been limited research on high-performance channel estimators in recent years. This study implemented a low-delay, low-overhead, relatively universal channel estimation module by dedicated instruction set acceleration including reference signal estimation, Wiener, 1st order, and 2nd order interpolations in frequency and time domains. The instruction level acceleration is on our vector processor, yet is suitable for other commercial and academic vector processors. Through instruction acceleration, compared with the existing general vector processing instruction sets, the processor performance of the LS estimation module and Wiener filter interpolation in the frequency domain is improved by 50% and 37.5%, respectively. The BER VS SNR measure of time–frequency Wiener filter interpolation achieves 4 db compared with linear interpolation, meaning our instruction level acceleration can be an optimum solution.

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Section: Channel Estimation At Pilotmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%