FPGA Implementation of Image Block Generation and Color Space Conversion for the Gaussian Mixture Model

Manu, K. S.; Rekha, K R; Nataraj, K. R.

doi:10.1109/icraect.2017.14

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…The feasibility of using MBFFs by inputting an RTL design during synthesis is presented by K. S. Manu et al (20) , and M. P. Lin,. (21) Design constraints, MBFF cells library, and the logic synthesis tool available is illustrated in Figure . 4.…”

Section: Mbffs Logic Optimizationmentioning

confidence: 99%

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

Rekha¹,

Nataraj²,

Rekha³

et al. 2021

IJST

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Objective:To analyze High-speed digital Integrated Circuit (IC) designing techniques and to identify the power dissipation rate in a different configuration of network switches. Methods: the complexity of a large-scale switching network is reduced using 2-bit Multi Bits Flip Flops (MBFF). The throughput and reliability are increased using a multibit flip-flop and have to be operated in parallel. The clock cycle required for 64-bit logical operation is analyzed using Xilinx software. The resources utilized during the execution process in various methods have been identified and analyzed Findings: Based on the survey, the proposed system will be built to identify characteristics of multi-bit flip flop based on switching speed (ps) concerning temperature (c), load capacity (fF), supply voltage (v), power consumption (mW) with respect to operating voltage (v) and many gates with respect to nanometer (nm) Novelty: Chip size and total power consumption rate by optimal chip reconfigurable network has been reduced to micrometer (mm) to nanometer (nm) and 0.3mW to 0.04mW respectively. Performance of parallel different applications operations in effective utilization of MBFF has been increased to 64 bits/s to 128 bits/s. The switching speed is increased with respect to clock frequency without any hazards and jitters using reconfigurable MBFF methods

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Section: Mbffs Logic Optimizationmentioning

confidence: 99%

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

Rekha¹,

Nataraj²,

Rekha³

et al. 2021

IJST

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show abstract

“…Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13,14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16,17]. The acquisition of real-time images has become an everyday task, using conventional cameras and stereo cameras for capturing in 3D [18,19], in which applications with digital programmable devices have been made to perform high-speed processing, achieving solutions where a single FPGA is used that replaces systems of multiple architectures that required connections and conversions of information, slowing down actions on processes in jobs where short response times are required [20,21].…”

Section: Introductionmentioning

confidence: 99%

Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED

2019

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This article shows the implementation of a system that uses a graphic interface to load a digital image into a programmable logic device, which is stored in its internal RAM memory and is responsible for visualizing it in a matrix of RGB LEDs, so that This way, the LEDs show an equivalent to the image that was sent from the PC, conserving an aspect ratio and respecting as much as possible the color of the original image. To carry out this task, a Matlab script was designed to load the image, convert and format the data, which are transmitted to the FPGA using the RS232 protocol. The FPGA is in charge of receiving them, storing them and generating all the signals of control and synchronization of the system including the control of the PWM signals necessary to conserve the brightness of each one of the LEDs. This system allows the visualization of static images in standard formats and, in addition, thanks to the flexibility of the hardware used, it allows the visualization of moving images type GIF.

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Design of Video Processing Platform with Interchangeable Input-Output Interfaces

Taron¹,

A²,

A³

et al. 2019

2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO)

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FPGA Implementation of Image Block Generation and Color Space Conversion for the Gaussian Mixture Model

Cited by 4 publications

References 10 publications

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED

Design of Video Processing Platform with Interchangeable Input-Output Interfaces

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