FPGA implementation of high performance FIR filters

Kollig, P.; Al-Hashimi, Bashir M.; Abbott, K.M.

doi:10.1109/iscas.1997.612767

Cited by 14 publications

(3 citation statements)

References 9 publications

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“…Section V el processing to I provides the d the obtained ns are drawn in nd. URE t exists between ucture for the ule limited by one where N is the the computation and is the then the critical s: (4) f the structure is (5) us the sampling and as the filter The critical path transposing the TRUCTURES y changing the nterchanging the The critical path computatio structure is given by:…”

Section: Transposed and Pipelined Stmentioning

confidence: 99%

“…The multiply operation is the main computational bottleneck in the FIR structure, requiring a high computation time [2]. A variety of approaches have been pursued to speed up the FIR filter structures [3] [4] [5]. Distributed arithmetic (DA) has been used as an alternative over the conventional Multiply and Accumulate (MAC) operations [6] [7].…”

Section: Introductionmentioning

confidence: 99%

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A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms

Khurshid

Mir

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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Numerical techniques have long been used to compute an approximate solution of a definite integral. The traditional approaches have mostly been software oriented. However, with the current trend moving back towards hardware intensive processing, it is desirable to develop a hardware oriented solution that assesses the performance in terms of some realistic parameters such as speed, power and area. This paper aims to exploit the one-to-one correspondence that exists between the Integration algorithms and the general FIR filters. Based on this correspondence a structure is developed that implements the Integration algorithm. However, typically such implementations have large critical path delays that put a limit on the resulting sampling/throughput rates. The paper addresses this problem by exploiting concurrency at various levels within the algorithm. Pipelined and parallel structures are developed and their effects on speed and power metrics are studied separately. It is shown that by these architectural modifications the data paths within the structure can be modified and the structure can be operated at higher throughput rates and/or with lower power consumption. Because of their ability to provide a high level of hardware programmability, FPGAs have been used as the implementation platform.

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Section: Transposed and Pipelined Stmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms

Khurshid

Mir

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

View full text Add to dashboard Cite

show abstract

“…The distribution graph concept based scheduling (PTS-MSE) algorithm given here is a parallel to the HLS scheduling algorithm given in [6]. It aims at achieving a balanced outcome merely by assessing the power-concurrency distribution graph (PCDG's) and the effect of block-testhestsubsession assignments by using a least mean square error (MSE) function.…”

Section: Distribution-graph-based Scheduling Approachmentioning

confidence: 99%