FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile WiMAX)

Harikrishna, K.; Rao, T. Rama; Labay, Vladimir A.

doi:10.7763/ijcte.2011.v3.305

Cited by 15 publications

(13 citation statements)

References 4 publications

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“…The common factor algorithm is formulated using Radix-2 2 and 3-dimensional liner index mapping. The Radix-2 2 common factor algorithm for 128-point is expressed as [5] -For 3-Dimensional Index Mapping -= 64 1 + 32 2 + 3…”

Section: Implementation Design Of the Proposed Fftmentioning

confidence: 99%

Implementation of fast FFT design for 128-point using Radix-22 CFA

Bansal

Nakhate

2018

IJET

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In this paper, implementation of fast FFT design for 128-point using Radix-2 2 CFA is presented. This research uses a common factor algorithm which is based on Radix-2 2 . A 2-point DFT butterfly structure is the lowest complexity structure and Radix-2 2 CFA is used to reduce logic and area by reducing the number of twiddle factors. The VHDL code is written and synthesized using Xilinx FPGA device xc7vx330t-3ffg1761 to implement the proposed design. This design is coded in VHDL and MATLAB. VHDL code is targeted to synthesize into Xilinx Virtex-7 FPGA and simulated into ModelSim PE Student Edition 10.4a. MATLAB code is simulated into MATLAB 2012. The proposed design achieves 149.822 MHz clock frequency, used 2802 slices on the Virtex-7 and SQNR 33.49 dB at 16-bit I/O word length.

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Section: Implementation Design Of the Proposed Fftmentioning

confidence: 99%

Implementation of fast FFT design for 128-point using Radix-22 CFA

Bansal

Nakhate

2018

IJET

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“…Reference [10] presents FPGA design, validation, and implementation of an OFDM modulator for IEEE-802.16e. In [11,12], OFDM implementations on the Xilinx Spartan 3 board are shown.…”

Section: State Of the Artmentioning

confidence: 99%

Towards Multi-gigabit OFDM Throughput on FPGA: Limitations and Challenges

Dokoski¹,

Tentov²

2014

Lecture Notes in Electrical Engineering

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This paper explores the possibility of achieving multi-gigabit data throughput over wireless networks, by using the FPGA technology. It focuses on the implementation complexity of an Orthogonal Frequency-Division Multiplexing (OFDM) modulation, as the most complex part of a physical layer in an 802.11 wireless network.The calculations are performed for a typical OFDM system, as synthesized in the Xilinx ISE Studio for the most popular Xilinx FPGA architectures. The results present the upper processing speeds that can be expected from an FPGA implementation of an OFDM modem.

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“…The correlator coefficients are computed by (2) and it should satisfy (3), (4) and (5). The coefficients are selected from the sequence of samples from short OFDM symbol and it is tabulated in Table 1.…”

Section: Design Of Direct Form Correlatormentioning

confidence: 99%

“…The important features of IEEE 802.16/WiMAX technologies are frequency < 11 GHz, data rate is up to 100 MHz and distance up to 20 km. The WiMAX physical layer is based on OFDM [1] [2]. It is used by commercial broadband systems such as DSL, Wi-Fi and media to enable high speed data, and multimedia applications.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power and High Speed Correlators for IEEE 802.16 WiMAX Systems

B¹,

Poongodi²

2016

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The advanced communication system uses wireless broadband access technologies which provide high speed data connectivity to the subscribers. One of the most popular wireless access technology is Worldwide Interoperability for Microwave Access (WiMAX) and it is based on IEEE 802.16 standard. WiMAX used Orthogonal Frequency Division Multiplexing (OFDM) is an effective modulation technique to improve the timing synchronization. The performance of channel is affected due to the synchronization mismatching between the transmitter and receiver ends. To achieve the timing synchronization in IEEE 802.16 systems, the cross correlator is used to synchronize the received signal with the known signal. In this paper, two high speed correlators are proposed based on Q1.15 format, which is used to validate the timing synchronization problem. The proposed work has been mapped on XC6VCX75T FPGA and simulations are carried out on the Xilinx-ISIM platform. The implementation result shows that the power delay product reduction is 40.81%, and delay reduction is 39.59% over the conventional multiplier less correlators.

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FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile WiMAX)

Cited by 15 publications

References 4 publications

Implementation of fast FFT design for 128-point using Radix-22 CFA

Implementation of fast FFT design for 128-point using Radix-22 CFA

Towards Multi-gigabit OFDM Throughput on FPGA: Limitations and Challenges

Design of Low Power and High Speed Correlators for IEEE 802.16 WiMAX Systems

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