2012
DOI: 10.1016/j.nima.2012.01.022
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FPGA implementation of digital constant fraction algorithm with fractional delay for optimal time resolution

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Cited by 10 publications
(2 citation statements)
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“…The variable delay that is necessary for different pulse shapes to obtain the best timing resolution makes its use even more difficult [13]–[14]. Although digital CFDs can be implemented inside an FPGA and can use variable delay lengths, this implementation needs a very fast analog-to-digital converter (ADC), which is power hungry and expensive [6], [15]. An LED with a low-level threshold applied to the leading edge of the signal is the simplest time pick-off method.…”
Section: Introductionmentioning
confidence: 99%
“…The variable delay that is necessary for different pulse shapes to obtain the best timing resolution makes its use even more difficult [13]–[14]. Although digital CFDs can be implemented inside an FPGA and can use variable delay lengths, this implementation needs a very fast analog-to-digital converter (ADC), which is power hungry and expensive [6], [15]. An LED with a low-level threshold applied to the leading edge of the signal is the simplest time pick-off method.…”
Section: Introductionmentioning
confidence: 99%
“…The TDPAC set-up mounted online consisted of four LaBr 3 gamma detectors with good energy resolution (11.6% at 84.1 keV and 3.0% at 637 keV) and time resolution of 800 ps for the selected cascade. Data acquisition was performed with the digital and FPGA signal processing DIGIPAC setup [18][19][20]. The detectors were positioned in a plane perpendicular to the direction of the radioactive beam, each detector placed at ±90 • and 180 • with respect to the others, as shown in fig.…”
mentioning
confidence: 99%