FPGA implementation of bidirectional associative memory via simultaneous perturbation rule

Wakamura, M.; Maeda, Yutaka

doi:10.1109/sice.2002.1196557

Cited by 3 publications

(7 citation statements)

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“…Winner-take-all networks, which utilize recurrent inhibitory connections to force a single output, have also been implemented in neuromorphic systems [1107]- [1109]. Hopfield networks were especially common in earlier neuromorphic implementations, as is consistent with neural network research at that time [5], [6], [13], [15], [759], [764], [813], [1110]- [1148], but there are also more recent implementations [838], [1149]- [1159]. Similarly, associative memory based implementations were also significantly more popular in earlier neuromorphic implementations [1053], [1160]- [1182].…”

Section: Network Modelsmentioning

confidence: 87%

“…Other approaches for on-chip supervised weight training have been utilized. These approaches include the least-mean-squares algorithm [750], [787], [1025], [1026], weight perturbation [19], [625], [655], [669], [682], [698], [699], [708], [710], [712], [713], [715], [736], [834], [835], [841], [845]- [847], [856], [1078]- [1080], [1098], [1099], [1148], [1304], training specifically for convolutional neural networks [1305], [1306] and others [169], [220], [465], [714], [804], [864], [865], [1029], [1049], [1307]- [1320]. Other on-chip supervised learning mechanisms are built for particular model types, such as Boltzmann machines, restricted Boltzmann machines, or deep belief networks [12], [627], [1135], [1193]<...>…”

Section: A Supervised Learningmentioning

confidence: 99%

“…The first is field programmable gate arrays or FPGAs. FPGAs have been frequently utilized in neuromorphic systems [86], [169], [192], [194], [200], [202], [206], [207], [217], [481], [489]- [570], [573], [575], [587], [588], [605], [617]- [619], [805], [806] [1106], [1139], [1141]- [1148], [1155]- [1159], [1179]- [1182], [1187]- [1192], [1209]- [1211], [1213], [1214], [1245]- [1248], [1267], [1268], [1277], [1279]- [1282], [1287], [1289], [1293], [1304], [1339]- [1348], …”

Section: A High-levelmentioning

confidence: 99%

“…N -bit parity tasks have also been commonly used [209], [217], [625], [657]- [659], [661], [680], [696], [697], [737], [855], [1092], [1193], [1346], [1349], [1883]- [1885], [2640], [2650], [2651]. Basic function approximation has also been a common task for neuromorphic systems, where a mathematical function is specified and the neuromorphic system is trained to replicate its output behavior [196], [419]- [421], [514], [518], [519], [614], [628], [643], [715], [819], [873], [874], [971], [983], [984], [1024], [1053], [1078], [1079], [1098], [1148], [1304], [1354], [1538], [2214],…”

Section: Applicationsmentioning

confidence: 99%

See 3 more Smart Citations

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

172

180

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Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brainlike ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled. The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed.

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Section: Network Modelsmentioning

confidence: 87%

Section: A Supervised Learningmentioning

confidence: 99%

Section: A High-levelmentioning

confidence: 99%

Section: Applicationsmentioning

confidence: 99%

See 2 more Smart Citations

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

172

180

View full text Add to dashboard Cite

show abstract

“…Consequently, this optimal allocation can be obtained by properly including different constraints (i.e., channel and queue status for the different users) in the definition of the HNN energy. From an implementation point of view, HNN methodology can be carried out either by solving iteratively a numerical differential equation based on the Euler technique or by means of hardware implementations (HNN is derived with an initial hardware implementation in mind) such as the field-programmable gate array (FPGA) chip [18] that has been proved practically for implementation purposes.…”

Section: Introductionmentioning

confidence: 99%

A New OFDMA Scheduler for Delay-Sensitive Traffic Based on Hopfield Neural Networks

Garcia

Pérez‐Romero

Agustí

2008

J Wireless Com Network

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This paper introduces a novel joint channel and queuing-aware OFDMA scheduler for delay-sensitive traffic based on a hopfield neural network (HNN) scheme. It allows providing an optimum OFDMA performance by solving a complex combinational problem. The algorithm is based on distributing the available subcarriers among the users depending, on the one hand, on the time left for the transmission of the different packets in due time, so that packet droppings are avoided. On the other hand, it also accounts for the available channel capacity in each subcarrier depending on the channel status reported by the different users. The different requirements are captured in the form of an energy function that is minimized by the algorithm. In that respect, the paper illustrates two different algorithms coming from two settings of this energy function. The algorithms have been evaluated for delay-sensitive traffic and they have been compared against other state-of-the-art algorithms existing in the literature, exhibiting a better behavior in terms of packet-dropping probability.

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Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Yeong,

2023

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Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

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FPGA implementation of bidirectional associative memory via simultaneous perturbation rule

Cited by 3 publications

References 0 publications

A Survey of Neuromorphic Computing and Neural Networks in Hardware

A Survey of Neuromorphic Computing and Neural Networks in Hardware

A New OFDMA Scheduler for Delay-Sensitive Traffic Based on Hopfield Neural Networks

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

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