FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors

Sairam, P; Manikumar, K; Reddy, Y Suresh; Narayana, B Uday; Gowreesrinivas, K.V.

doi:10.1109/devic57758.2023.10134837

2023 IEEE Devices for Integrated Circuit (DevIC) 2023

DOI: 10.1109/devic57758.2023.10134837

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FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors

P Sairam,

K Manikumar,

Y Suresh Reddy

et al.

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FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors

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