FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links

Abstract

In this paper, an FPGA implementation of a Multi Input Multi Output (MIMO) Decision Feedback equalizer (DFE) is proposed, for the electronic compensation of the impairments in 40Gb/s Intensity Modulated Direct Detection (IM/DD) optical communication links employing NRZ DQPSK signaling. The proposed equalizer is used for the electronic compensation the residual Chromatic Dispersion (CD) along the installed optically compensated optical paths. The required processing rate is achieved by applying intensive pipelining and parallelism in the original architecture of the equalizer. At the given processing rate, a 8-input 2-output DFE involving three taps feedforward filtering and two taps backward filtering is implemented on a single, cutting edge technology, Xilinx FPGA device.

High-Speed, High-Performance DQPSK Optical Links with Reduced Complexity VDFE Equalizers

“…As shown in previous work [2,12,20,25] the amount of dispersion that an equalizer can compensate is directly related to both the memory of the FF and FB filters. As the values of and increase, the performance of the equalizer in compensating chromatic dispersion improves.…”

“…The feasibility of the implementation of those methods on FPGA (Field-Programmable Gate Array) circuitry has recently been demonstrated [2,12,20], for rates up to 40 Gb/s. Due to the joint constructive/destructive processing, four signals are available as input to the equalizer.…”

“…VDFE employing skimmed Volterra kernels in place of the full-sized counterparts, have been proposed as a viable solution in high-speed, low-cost implementation for the equalization of OOK keying signaling, as well as for the DQPSK modulation, operating at bit rates as high as 40 Gb/s [2,10,12,20]. Assuming the same example of Equation (4), let the signals processed given by the triplet (I c , Q c , Q d ), i.e., the destructive port of the I channel, be ignored.…”