FPGA Implementation of 5G NR LDPC Codes

Abstract

As a result of rising expectations for quality, the employment of advanced technical requirements for future fifth-generation (5G) new radio is required. The error-correction coding method is one of the most important components of a new generation. The 5G NR New Radio Low-Density Parity Check (LDPC) codes, which have been adopted by the 5G standard, are a standout solution in terms of high coding gain, high throughput, and low power dissipation. This paper presents an implementation of 5th generation (5G) New Radio (NR) and 5G NR low-density parity check codes, which are performed with the aid of a proper architecture. LABVIEW will be used in wireless communications to reduce the cost, space, and power. Simultaneously, this increased the speed. The circuit design supports a constraint length of 1360 and a code rate of 0.5. The LDPC encoder and decoder are implemented on an NI MY RIO 1900 ZYNQ FPGA at a 33 MHZ core frequency starter kit. Xilinx Vivado 18.2 series was used for the simulation. The implemented design shows an area overhead reduction of 50% compared with the referenced designs of the Xilinx 7 series device. In MY RIO ZYNQ, the proposed method achieved 21000 LUTs compared with Xilinx 7-series solutions, and it has a much higher throughput (224 vs. 87 and 5 MBit/s), followed by MY RIO ZYNQ, which is better than previous state-of-the-art solutions in terms of area and higher data rates. Moreover, the implemented 5G NR LDPC decoder tested against an additive white Gaussian noise channel (AWGN) and consequently has gained more popularity in many applications.