FPGA Implementation for Elliptic Curve Cryptography Algorithm and Circuit with High Efficiency and Low Delay for IoT Applications

Abstract

The Internet of Things requires greater attention to the security and privacy of the network. Compared to other public-key cryptosystems, elliptic curve cryptography can provide better security and lower latency with shorter keys, rendering it more suitable for IoT security. This paper presents a high-efficiency and low-delay elliptic curve cryptographic architecture based on the NIST-p256 prime field for IoT security applications. A modular square unit utilizes a fast partial Montgomery reduction algorithm, demanding just a mere four clock cycles to complete a modular square operation. The modular square unit can be computed simultaneously with the modular multiplication unit, consequently improving the speed of point multiplication operations. Synthesized on the Xilinx Virtex-7 FPGA platform, the proposed architecture completes one PM operation in 0.08 ms using 23.1 k LUTs at 105.3 MHz. These results show significantly better performance compared to that in previous works.

DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

“…The designs described in [6], [11]- [13] are centered around the Weierstrass ECC model operating within a GF (2 m ) field. The design of [14] describes a hardware accelerator for FPGA devices, where a Weierstrass ECC model over a GF (P ) field, with P = 256, has been implemented. The BHC curve is considered for hardware acceleration in designs of [15], [16].…”

“…Instead of hardware accelerators of [6], [11]- [13], [15] over binary field lengths, prime field over GF (P ) with P = 256 is considered in [14], [17], [19] for hardware acceleration. One accelerator over special ECC Curve448 is described in [21].…”

“…One accelerator over special ECC Curve448 is described in [21]. On identical Virtex-7 FPGA, the utilized LUTs in [14] are 1.90 (a ratio of 23k to 12113) times higher than our hardware accelerator. In other words, our accelerator is indeed more area-efficient than the reference prime field accelerator.…”

“…In other words, our accelerator is indeed more area-efficient than the reference prime field accelerator. No doubt, the potential reason is the supported key length; we utilized a 233-bit binary field, while the design of [14], considers a prime field of length 256. Instead of the area, we surpass operating frequency, latency, throughput, and FoM values, as evident in Table 2.…”

Throughput/Area-Efficient Accelerator of Elliptic Curve Point Multiplication over GF(2233) on FPGA

“…The Weierstrass, binary Huff curves (BHCs), Hessian, and binary Edward curves (BECs) are various ECC models. Therefore, the most related state-of-the-art hardware accelerators are described in [6,[10][11][12][13][14][15][16][17][18][19]. Reference [6] proposes a pipelined architecture to accelerate ECPM operation by reducing the critical path delay.…”