2012
DOI: 10.1007/978-3-642-30223-7_54
|View full text |Cite
|
Sign up to set email alerts
|

FPGA Implementation and Verification System of H.264/AVC Encoder for HDTV Applications

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2012
2012
2022
2022

Publication Types

Select...
2
1

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(1 citation statement)
references
References 4 publications
0
1
0
Order By: Relevance
“…Different works are available in the state-of-the-art about FPGA implementations of the H.264 encoder, but focusing in particular stages whose performance is critical, such as motion estimation [9], [10], [11], [12], the intra-prediction [13], [14], quantization [15] or the encoding [16], [17]. A full hardware implementation of the H.264 encoder in baseline profile is presented in [18], consuming the 89% of slices available in a Xilinx XC6VLX240T FPGA.…”
Section: Introductionmentioning
confidence: 99%
“…Different works are available in the state-of-the-art about FPGA implementations of the H.264 encoder, but focusing in particular stages whose performance is critical, such as motion estimation [9], [10], [11], [12], the intra-prediction [13], [14], quantization [15] or the encoding [16], [17]. A full hardware implementation of the H.264 encoder in baseline profile is presented in [18], consuming the 89% of slices available in a Xilinx XC6VLX240T FPGA.…”
Section: Introductionmentioning
confidence: 99%