FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator

El-Maksoud, Ahmed J. Abd; Mohamed, Abdalla; Tarek, Ahmed; Adel, Amr; Eid, Amr; Khaled, Farida; Khaled, Fatma; Ibrahim, Ziad; Mandouh, Eman El; Mostafa, Hassan

doi:10.1109/niles53778.2021.9600555

Cited by 2 publications

(5 citation statements)

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“…Table 3 presents a performance comparison with related works. The hardware resource utilization, particularly in BRAM and DSP, in [ 35 ] is quite high compared to those of [ 37 ], leading to high power consumption according to the total on-chip power in [ 38 ]. The BRAM and DSP consumed approximately 60% of the total power.…”

Section: Resultsmentioning

confidence: 99%

“…To deploy deep learning hardware accelerators on edge devices, the hardware size must be small with a lightweight design owing to limited resource constraints. However, the hardware size of [ 36 ] and [ 38 ] is too large over thousands for all components, 324.7 k and 315.4 k as LUT, FF for [ 36 ], and 135.5 k as FF for [ 38 ] in VC709. The BRAM and DSP utilization is also high, so their power consumption is quite high as 27.7 W for [ 36 ] and 8.9 W for [ 38 ].…”

Section: Resultsmentioning

confidence: 99%

“…However, the hardware size of [ 36 ] and [ 38 ] is too large over thousands for all components, 324.7 k and 315.4 k as LUT, FF for [ 36 ], and 135.5 k as FF for [ 38 ] in VC709. The BRAM and DSP utilization is also high, so their power consumption is quite high as 27.7 W for [ 36 ] and 8.9 W for [ 38 ]. They are not able to be embedded in resource-constrained edge devices because of an enormous amount of hardware utilization and cannot be operated on battery-operated IoT devices because they require high power consumption.…”

Section: Resultsmentioning

confidence: 99%

“…Many studies on accelerating SqueezeNet on FPGA have been introduced in the literature [ 35 , 36 , 37 , 38 , 39 ]. In [ 35 ], the authors attempted to enhance the performance of the hardware processing convolution operation through pipelining and loop unrolling and flattening.…”

Section: Introductionmentioning

confidence: 99%

“…A high-speed hardware accelerator was implemented in [ 38 ]. The researchers used a ping-pong memory strategy and deployed several first-in, first-outs (FIFOs) in their design to solve the memory bottleneck issue.…”

Section: Introductionmentioning

confidence: 99%

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Lightweight and Energy-Efficient Deep Learning Accelerator for Real-Time Object Detection on Edge Devices

Jang

Park

Lee

et al. 2023

Sensors

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Tiny machine learning (TinyML) has become an emerging field according to the rapid growth in the area of the internet of things (IoT). However, most deep learning algorithms are too complex, require a lot of memory to store data, and consume an enormous amount of energy for calculation/data movement; therefore, the algorithms are not suitable for IoT devices such as various sensors and imaging systems. Furthermore, typical hardware accelerators cannot be embedded in these resource-constrained edge devices, and they are difficult to drive real-time inference processing as well. To perform the real-time processing on these battery-operated devices, deep learning models should be compact and hardware-optimized, and hardware accelerator designs also have to be lightweight and consume extremely low energy. Therefore, we present an optimized network model through model simplification and compression for the hardware to be implemented, and propose a hardware architecture for a lightweight and energy-efficient deep learning accelerator. The experimental results demonstrate that our optimized model successfully performs object detection, and the proposed hardware design achieves 1.25× and 4.27× smaller logic and BRAM size, respectively, and its energy consumption is approximately 10.37× lower than previous similar works with 43.95 fps as a real-time process under an operating frequency of 100 MHz on a Xilinx ZC702 FPGA.

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Section: Resultsmentioning

confidence: 99%