FPGA-Based Symmetric Re-Encryption Scheme to Secure Data Processing for Cloud-Integrated Internet of Things

Al-Asli, M.; Elrabaa, Muhammad E. S.; Abu-Amara, Marwan

doi:10.1109/jiot.2018.2864513

Cited by 26 publications

(9 citation statements)

References 36 publications

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“…The proposed scheme gives efficient and accurate processing logs. To protect the IoT processing from internal attacks, again an FPGA‐based scheme is proposed in Al‐Asli et al, 37 in which authors presented a cloud‐based business model approach for symmetric re‐encryption to secure data processing. According to the author, while transferring a ciphertext of size 1 Gb, the experimental results of FPGA based proposed scheme gives 6 times faster results than the SW implementation.…”

Section: Related Workmentioning

confidence: 99%

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

Qureshi

Qayyum

Islam

et al. 2021

Circuit Theory & Apps

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Summary Technologies and new standards have converted the traditional networks and systems into new smart cities integrated networks. Different factors are behind to build these new networks in terms of hardware, software, standards, technologies, and infrastructure. Internet of things (IoT) is one of the popular network types based on small and portable devices. Some of the IoT applications are more critical and sensitive like smart healthcare systems wherein time data delivery is needed without any delay. Keeping in view the criticality of such applications, this study proposes a secure storage, processing and transmission (SSPT) technique. This technique is based on two modules named Advanced Encryption Standard (AES) in Electronic Code Book (ECB) mode and AES in Ciphered Message Authentication Code (CMAC) mode. In the first module, the AES is implemented in ECB mode to provide encryption to IoT computer vision data. In the second module, the AES is integrated with the CMAC algorithm to provide encryption, integrity, and authentication. The said modules are implemented in a field programmable gate array (FPGA) device which acts as a secure edge computing device. The SSPT is verified by the test vectors given by international standards such as the National Institute of Standards and Technologies (NIST) and Federal Information Processing Standards (FIPS) which are adaptable, proficient, and vigorous as compared to previous techniques.

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Section: Related Workmentioning

confidence: 99%

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

Qureshi

Qayyum

Islam

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

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“…Al-Asli [19] presented FPGA based symmetric re-encryption scheme to secure the data processing for cloud-integrated IoT. The proposed scheme supports various business models involving multiple parties and the data owner to give temporary access to IoT data to specific clients at a public market place (the cloud).…”

Section: Related Workmentioning

confidence: 99%

A Non Linear PUF Circuit Design for Two Factor Authentication in IoT Cryptography

Gurumanapalli¹,

Muthuluru²

2021

IJIES

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Internet-of-Things (IoT) is growing network paradigm which enables mutual communication between the user and smart devices using the internet. The IoT devices are susceptible to the security threats, due to placement of restricted computational capabilities of the computing devices in IoT. The conventional encryption algorithm utilizes the high amount of resource block in it which increases the area and power. Moreover, Two Factor Authentication (TFA) scheme based authentication protocols does not have the efficiency to secure the data. Because the random number generated by the TFA is ideal for all IoT devices which are easy to hack by the unauthorized persons. In this Research paper, the Linear Feedback Shift Register (LFSR) based Reconfigurable Physical Unclonable Function (RPUF) is proposed to overcome the security issues caused in the IoT communication. The RPUF is designed based on the LFSR to generate the random number for every clock cycle. Normally, reconfigurable process helps to generate the different output values for every clock cycle. But, it failed to generate different outputs for same input values. Here, LFSR based RPUF helps to generated the different response values even the same challenge is given to the input side. The Lightweight TFA scheme is presented for IoT, where PUF has been considered as one of the major authentication factors. At last, Spartan 6 and Virtex 6 Field Programmable Gate Array (FPGA) performances are calculated for proposed TFA-RPUF-IoT and existing TFA-PUF-IoT protocols. In Spartan 6, TFA-RPUF-IoT protocol occupied 11 slices, 31 LUTs, 42 flip flops which are less compared to conventional TFA-PUF-IoT.

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“…FPGA chips can operate simultaneously and it has a comparatively flexible architecture. Hence, the test cycles and design cost of the FPGA chips are lower [31][32][33][34]. Since two different LUT-based methods, namely substitution box (S-Box) and T-box, are used for an effective design of AES over the FPGA, LUT-based encryption and decryption are not only memory intensive but also asymmetric because of its transformation sequence and AES functions of encryption and decryption.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Kumar

Balmuri²,

Marchewka

et al. 2021

Sensors

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Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

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FPGA-Based Symmetric Re-Encryption Scheme to Secure Data Processing for Cloud-Integrated Internet of Things

Cited by 26 publications

References 36 publications

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

A Non Linear PUF Circuit Design for Two Factor Authentication in IoT Cryptography

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

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