FPGA-Based Single-Phase PV Inverter Using Unipolar and Bipolar SPWM Control Techniques

Abstract

Investigation of FPGA-based SPWM generator as a control mechanism for a PV/Battery full-bridge inverter  The unipolar SPWM technique produces less harmonic distortion than the Bipolar method, with THD 45% lower  The system implementation of SPWM Pulse generation has been validated on Xilinx Spartan 6 FPGA (XC6SLX45) board using VHDL code. The study presents circuitry modeling and methodology to integrate solar photovoltaic (PV) energy with grid (AC) sources to supplement household appliances during a power cut-off or restricted supply period and alternating charge deep cycle batteries. This paper discusses an FPGA-based Sinusoidal Pulse Width Modulation (SPWM) generator as a control mechanism for a PV/Battery full-bridge inverter. The inverter's efficacy is expressed as the Total Harmonic Distortion (THD) ratio, which must be as low as possible. Various schemes are proposed to reduce THD to generate a more sinusoidal output wave. SPWM is mostly used in industrial inverters. Two SPWM techniques, Bipolar and unipolar, are compared under a variety of Modulation Index (MI) conditions and Carrier Frequency (fc) to analyze the best performance of the full-bridge inverter with less (THD) and smoother output sinewave. The present paper discusses the results of a simulation for a single-phase full-bridge inverter employing bipolar and unipolar SPWM techniques. The output waveform demonstrates that the Unipolar SPWM technique produces less Total harmonic Distortion than the Bipolar method, with THD 45% lower. ISE 14.7 and Matlab 2019 are used to present, simulate SPWM generating code, and implement the design on a field-programmable gate array (FPGA), which acts as a controller for the Mosfet gates in the full-bridge inverter to constitute a sine wave without changing any hardware configuration in the circuit design. The system implementation of SPWM Pulse generation has been validated on Xilinx Spartan 6 FPGA (XC6SLX45) board using VHDL code. The final test on the system design for the SPWM generation program, after synthesis and compilation were finalized and verified on a prototype system.