FPGA-Based Selected Object Tracking Using LBP, HOG and Motion Detection

Sledevie, Tomyslav; Serackis, Artūras; Plonis, Darius

doi:10.1109/aieee.2018.8592410

Cited by 9 publications

(7 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some researchers use pre-developed IP cores for magnitude calculation in the HOG algorithm. Sledeviè et al [25], FIGURE 7. A basic hardware architecture for magnitude approximation.…”

Section: B Magnitude Calculationmentioning

confidence: 99%

“…Sledeviè et al [25] increase the number of HOG features by using pixels which are one pixel further from the center pixel. Their implementation uses both the 8 pixels around the main pixel and the 16 pixels around the first 8 pixels to compute the gradient, and this method processes 24 pixels for each pixel.…”

Section: Gradient Extensionmentioning

confidence: 99%

“…Fig. 11 shows the histogram bins for one pixel using the method provided by Sledeviè et al [25]. Higher accuracy is expected by using more features to get more information about the local variations of the image.…”

Section: Gradient Extensionmentioning

confidence: 99%

“…We compute this metric only for papers that reported the frame size, the clock frequency of the FPGA, and frames per second rate. As shown in Table 4, some work use Zynq family FPGAs [7], [10], [16], [21], [24], [15] while others use Virtex series FPGAs [1], [3]- [5], [9], [11], [17], [25], [35]. On the other hand, [2], [20], [26]- [28] use Cyclone family FPGAs.…”

Section: A Speed Comparisonmentioning

confidence: 99%

“…A complete object detection model can be designed by using HOG features coupled with a classifier such as Adaboost [1] or Support Vector Machines [2], [3]. Some work focus on modified extended features based on HOG descriptors [11], [25].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Analysis and Comparison of FPGA-Based Histogram of Oriented Gradients Implementations

Ghaffari

Soleimani

et al. 2020

IEEE Access

View full text Add to dashboard Cite

One of the commonly-used feature extraction algorithms in computer vision is the histogram of oriented gradients. Extracting the features from an image using this algorithm requires a large amount of computations. One way to boost the speed is to implement this algorithm on field programmable gate arrays, to benefit from flexible designs such as parallel computing. In this paper, we first, provide a summary of the steps of the histogram of oriented gradients algorithm. We then survey the implementation techniques of the histogram of oriented gradients on field-programmable gate arrays in the past decade. We group the different techniques into four main categories and analyze various enhancement methods in each category. The first group is the optimization of the algorithm computation which involves the steps of input selection, magnitude calculation, orientation and bin assignment, and normalization. The second category is data manipulation techniques which include numerical representation, data flow modification, and memory optimization. The third group contains modified features based on the histogram of oriented gradients and their hardware implementation, and the fourth one is the implementations in hardware-software co-design of the algorithm. We compare the different implementations using a speed metric called pixels per clock cycle, and resource utilization. Finally, we provide design summary tables for efficient implementation with respect to the speed metric, accuracy, and resource utilization. INDEX TERMS Histogram of oriented gradients, field programmable gate arrays, hardware acceleration, hardware design. KIN FUN LI is the Director of the two highly sought-after professional master of engineering programs in telecommunications and information security (MTIS) and applied data science (MADS) at the University of Victoria, Canada, where he teaches both hardware and software courses in the Department of Electrical and Computer Engineering. He dedicates his time to instructing and researching in computer architecture, hardware accelerators, education analytics, and data mining applications. He is actively involved in the organization of many international conferences, including the biennial IEEE Pacific Rim in Victoria and the internationally held IEEE AINA. He is also a passionate supporter and participant in numerous international activities to promote the engineering profession, education, and diversity.

show abstract

“…Some researchers use pre-developed IP cores for magnitude calculation in the HOG algorithm. Sledeviè et al [25], FIGURE 7. A basic hardware architecture for magnitude approximation.…”

Section: B Magnitude Calculationmentioning

confidence: 99%

Section: Gradient Extensionmentioning

confidence: 99%

Section: Gradient Extensionmentioning

confidence: 99%

Section: A Speed Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analysis and Comparison of FPGA-Based Histogram of Oriented Gradients Implementations

Ghaffari

Soleimani

et al. 2020

IEEE Access

View full text Add to dashboard Cite

show abstract

Intelligent video analysis for enhanced pedestrian detection by hybrid metaheuristic approach

Preethaa

Sabari²

2020

Soft Comput

View full text Add to dashboard Cite

High‐speed target tracking algorithm for the pulse‐sequence‐based image sensor

Wang

Gao

et al. 2020

IET Image Processing

View full text Add to dashboard Cite

This paper proposed a high-speed target tracking algorithm based on the pulse-sequencebased image sensor. The algorithm separates the target from the background through the statistical distribution of the pulses in a single frame of data. In order to achieve more accurate target tracking, the phenomenon of image lag in the process of capturing the high-speed moving target is studied. The positioning deviation is compensated by estimating the image lag length of the moving target. The algorithm is implemented with pipeline processing on field-programmable gate array (FPGA). The positioning accuracy of the algorithm is verified with input data from a pulse-sequence image sensor model. The verification results show that the maximum position deviation of the target at different speeds is 0.94 pixels. In the experiment of tracking a 40 m/s moving ball, this algorithm can provide real-time position information within 44 ns.

show abstract

FPGA-Based Selected Object Tracking Using LBP, HOG and Motion Detection

Cited by 9 publications

References 8 publications

Analysis and Comparison of FPGA-Based Histogram of Oriented Gradients Implementations

Analysis and Comparison of FPGA-Based Histogram of Oriented Gradients Implementations

Intelligent video analysis for enhanced pedestrian detection by hybrid metaheuristic approach

High‐speed target tracking algorithm for the pulse‐sequence‐based image sensor

Contact Info

Product

Resources

About