FPGA-based pedestrian detection under strong distortions

Tasson, D.; Montagnini, Anna; Marzotto, R.; Farenzena, Michela; Cristani, Marco

doi:10.1109/cvprw.2015.7301368

Cited by 12 publications

(4 citation statements)

References 14 publications

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“…In [ 12 ], Z. Ling et al developed a system to estimate the position of the head, achieving a rate of 16 fps with 68 landmarks and their experiments run on an Altera Cyclone V FPGA. In [ 13 ], an FPGA-based pedestrian detection approach under strong distortions is presented.…”

Section: Introductionmentioning

confidence: 99%

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application

Christakos

Petrellis

Mousouliotis

et al. 2023

Sensors

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A high-performance Driver State Monitoring (DSM) application for the detection of driver drowsiness is presented in this paper. The popular Ensemble of Regression Trees (ERTs) machine learning method has been employed for the alignment of 68 facial landmarks. Open-source implementation of ERTs for facial shape alignment has been ported to different platforms and adapted for the acceleration of the frame processing speed using reconfigurable hardware. Reducing the frame processing latency saves time that can be used to apply frame-to-frame facial shape coherency rules. False face detection and false shape estimations can be ignored for higher robustness and accuracy in the operation of the DSM application without sacrificing the frame processing rate that can reach 65 frames per second. The sensitivity and precision in yawning recognition can reach 93% and 97%, respectively. The implementation of the employed DSM algorithm in reconfigurable hardware is challenging since the kernel arguments require large data transfers and the degree of data reuse in the computational kernel is low. Hence, unconventional hardware acceleration techniques have been employed that can also be useful for the acceleration of several other machine learning applications that require large data transfers to their kernels with low reusability.

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Section: Introductionmentioning

confidence: 99%

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application

Christakos

Petrellis

Mousouliotis

et al. 2023

Sensors

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show abstract

“…In [9], Z. Ling et al developed a system to estimate the position of the head, achieving a rate of 16fps with 68 landmarks and their experiments are running on an Altera Cyclone V FPGA. In [10], an FPGA-based pedestrian detection approach under strong distortions is presented.…”

Section: Introductionmentioning

confidence: 99%

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application

Christakos¹,

Petrellis²,

Mousouliotis³

et al. 2023

Preprint

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A high performance Driver State Monitoring (DSM) application for the detection of driver drowsiness is presented in this paper. It relies on the usage of an Ensemble of Regression Trees (ERTs) machine learning method that aligns 68 facial landmarks. Special focus is given on the acceleration of the frame processing using reconfigurable hardware. Reducing the frame processing latency saves time that can be used to apply frame-to-frame facial shape coherency rules. False face detection and false shape estimations can be ignored for higher robustness and accuracy in the operation of the DSM application without reducing the frame processing rate that can reach 65 frames per second. The sensitivity and precision in yawning recognition can reach 93% and 97%, respectively. The implementation of the employed DSM algorithm in reconfigurable hardware is challenging since the kernel arguments require large data transfers and the degree of data reuse in the computational kernel is low. Due to this, unconventional hardware acceleration techniques have been employed that can also be useful for the acceleration of several other applications.

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“…Since HOG is a computationally intensive algorithm, it has been implemented on different platforms, such as graphical processors (GPUs) and more recently on Field-Programmable Gate Arrays (FPGAs). The latter have superior performance in terms of cost, speed, and power consumption [11,12]. All these aspects are essential for commercial applications in general and in particular for enabling classification systems that can work at high vehicle speed.…”

Section: Introductionmentioning

confidence: 99%

A New Method of Histogram Computation for Efficient Implementation of the HOG Algorithm

Ilas

2018

Computers

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In this paper we introduce a new histogram computation method to be used within the histogram of oriented gradients (HOG) algorithm. The new method replaces the arctangent with the slope computation and the classical magnitude allocation based on interpolation with a simpler algorithm. The new method allows a more efficient implementation of HOG in general, and particularly in field-programmable gate arrays (FPGAs), by considerably reducing the area (thus increasing the level of parallelism), while maintaining very close classification accuracy compared to the original algorithm. Thus, the new method is attractive for many applications, including car detection and classification.

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FPGA-based pedestrian detection under strong distortions

Cited by 12 publications

References 14 publications

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application

A New Method of Histogram Computation for Efficient Implementation of the HOG Algorithm

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