FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application

New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application

“…But these codes need complicated decoding circuitry and have higher delay which make their design more gate-intensive. Tripathi et al have implemented an efficient multi-bit adjacent ECC for memory [11]. Also, Moran et al presented a flexible unequal error correction codes.…”