FPGA-based High-speed True Random Number Generator for Cryptographic Applications

Kwok, Siew-Hwee; Lam, E.Y.

doi:10.1109/tencon.2006.344013

Cited by 37 publications

(21 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are several classic methods developed during this period. Typically, we can categorize them into analogue [4], digital [6] and mixed-signal based [5]. Fig.…”

Section: A Related Workmentioning

confidence: 99%

“…In the past years, several methods have been presented by the researchers to achieve a digital based TRNG circuit. In general, the most popular candidates of the randomness source is the jitter of the digital clock resource, including the free-running ring oscillator (RO), phase lock loop (PLL) or delay lock loop (DLL) [5], the meta-stability behavior, and the noises in the circuit, etc. Among these works, the most cited one is the design proposed by Sunar et al [6].…”

Section: A Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A complementary architecture for high-speed true random number generator

Xian

Cheung

2014

2014 International Conference on Field-Programmable Technology (FPT)

View full text Add to dashboard Cite

In this paper, we introduce a novel FPGA-based design for true random number generator (TRNG). It is able to harvest the timing difference caused by the nonuniformity of the Integrated Circuits (ICs) and use it to generate the randomness. Compared with the previous related work, this design uses a complementary scheme that leads to a doubled data rated output. The proposed complementary design has improved entropy and achieved higher throughput. The prototype design has been implemented and verified on a Xilinx Virtex-6 ML605 evaluation board. As a result, the generated random number stream is able to pass the statistical NIST and DIEHARD test suites showing a reliable performance. Meanwhile, it can approach the maximum data rate as 50 Mbps stably.

show abstract

“…There are several classic methods developed during this period. Typically, we can categorize them into analogue [4], digital [6] and mixed-signal based [5]. Fig.…”

Section: A Related Workmentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

A complementary architecture for high-speed true random number generator

Xian

Cheung

2014

2014 International Conference on Field-Programmable Technology (FPT)

View full text Add to dashboard Cite

show abstract

“…This circuit passed NIST test with Altera APEX 20K FPGA and Stratix FPGA. Likewise, Kwok and Lam [7] proposed a TRNG, which utilizes a DCM (digital clock manager) of Xilinx Virtex II Pro FPGA to generate the second clock signal. It is obvious that an onchip PLL (or its equivalent) is indispensable for this kind of TRNG; meanwhile, this work presents a TRNG that consists of fundamental logic gates only.…”

Section: Related Studiesmentioning

confidence: 99%

FPGA Implementation of Metastability-Based True Random Number Generator

Hata

Ichikawa

2012

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYTrue random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in freerunning ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with fullcustom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.

show abstract

“…Otherwise, we can build one ourselves. There are many works which propose PRNG or TRNG implementation for both ASIC [Cui et al 2002;Tokunaga et al 2008;Zhun and Hongyi 2001] and FPGA [Danger et al 2007;Klein et al 2008;Kwok and Lam 2007;Schellekens et al 2006]. We used FPGA implementations in this work.…”

Section: Random Number Generationmentioning

confidence: 99%

An architecture-independent instruction shuffler to protect against side-channel attacks

Bayrak

Velickovic

Ienne

et al. 2012

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Embedded cryptographic systems, such as smart cards, require secure implementations that are robust to a variety of low-level attacks. Side-Channel Attacks (SCA) exploit the information such as power consumption, electromagnetic radiation and acoustic leaking through the device to uncover the secret information. Attackers can mount successful attacks with very modest resources in a short time period. Therefore, many methods have been proposed to increase the security against SCA. Randomizing the execution order of the instructions that are independent, i.e., random shuffling, is one of the most popular among them. Implementing instruction shuffling in software is either implementation specific or has a significant performance or code size overhead. To overcome these problems, we propose in this work a generic custom hardware unit to implement random instruction shuffling as an extension to existing processors. The unit operates between the CPU and the instruction cache (or memory, if no cache exists), without any modification to these components. Both true and pseudo random number generators are used to dynamically and locally provide the shuffling sequence. The unit is mainly designed for in-order processors, since the embedded devices subject to these kind of attacks use simple in-order processors. More advanced processors (e.g., superscalar, VLIW or EPIC processors) are already more resistant to these attacks because of their built-in ILP and wide word size. Our experiments on two different soft in-order processor cores, i.e., OpenRISC and MicroBlaze, implemented on FPGA show that the proposed unit could increase the security drastically with very modest resource overhead. With around 2% area, 1.5% power and no performance overhead, the shuffler increases the effort to mount a successful power analysis attack on AES software implementation over 360 times.

show abstract

FPGA-based High-speed True Random Number Generator for Cryptographic Applications

Cited by 37 publications

References 1 publication

A complementary architecture for high-speed true random number generator

A complementary architecture for high-speed true random number generator

FPGA Implementation of Metastability-Based True Random Number Generator

An architecture-independent instruction shuffler to protect against side-channel attacks

Contact Info

Product

Resources

About