FPGA based High Speed Memory BIST Controller for Embedded Applications

Ahmed, Mohammed Altaf; Rani, D. Elizabeth; Sattar, Syed Abdul

doi:10.17485/ijst/2015/v8i33/76080

Cited by 7 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This worldwide trademark may be supportive for repairing bunch faults. In view of the recommended worldwide excess architectures, a heulandite modified essential spare pivoting (MESP) algorithm suitableness for BISR will be suggested [6]. The range overhead to actualizing that MESP algorithm is extremely low for less demanding discourse of the recommended strategies [11].…”

Section: Proposed Methodsmentioning

confidence: 99%

Global block level redundancy scheme for repair of clustered fault cells

Poornachandra¹

2019

IJATCSE

View full text Add to dashboard Cite

Spare full rows and columns are used in conventional memories to take care of any bad cells in memories. But this is not efficient as many chips do not become usable. Alternatively the spare redundant rows and redundant columns are bifurcated into blocks and block level repair can be attempted. A novel global feature is added to the spare blocks which enables the spare row(column) block to be used anywhere in the memory array. This memory hardware architecture can easily interface with embedded memory cores. A new algorithm, Essential Most Spare Pivoting (EMSP) is proposed which can be easily implemented in built-in configuration. The overhead area proposed in this paper is very less. The chip yield, reliability and repair rate are likely to improve significantly as per the simulation results.

show abstract

Section: Proposed Methodsmentioning

confidence: 99%

Global block level redundancy scheme for repair of clustered fault cells

Poornachandra¹

2019

IJATCSE

View full text Add to dashboard Cite

show abstract

“…More storage will expose prone to a fault [1]. It results in difficulties in testing memories in terms of failures [2,3]. As the survey reference to report of ITRS (International Technological Roadmap for Semiconductor) conducted by Semiconductor Industry Association (SIA), the portion of memory in SoC is above 95 % of the total area [4].…”

Section: Introductionmentioning

confidence: 99%

Memory test and repair technique for SoC based devices

Ahmed

Eljialy

Ahmad

2021

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

System on Chip (SoC) architecture mainly consists of the memories in a larger area. Due to the availability of memories in a largersize, it is difficult to test these memories for faults. Therefore, a smooth test solution to test these memories against fault and repair the faulty cells has introduced. In this research, we proposed a Memory Test Controller (MTC) to test the memories and Built-in Self-repair (BISR) mechanism to repair the faulty cells for any recent SoC based devices. The MTC not only identifies the fault, but it finds the type of fault available, and BISR block repairs the detected faulty cells. The paper provides empirical insights about how change is brought in features of the SoC based device after integrating both the proposed controller block. It is noticed that from the obtained results, the proposed methods are stands better in terms of the area overhead, power and timing when compared with the existing approaches.

show abstract

“…It keeps processor in an idle state and use DMA controller to transfer volume of data. The Virtex7 FPGA is used to implement the design [11]. Two case studies have presented to compare the performance of DMAC with processor.…”

Section: Introductionmentioning

confidence: 99%

Amba Based Advanced DMA Controller for SoC

Aljumah¹,

Ahmed²

2016

ijacsa

View full text Add to dashboard Cite

Abstract-this paper describes the implementation of an AMBA Based Advanced DMA Controller for SoC. It uses AMBA Specifications, where two buses AHB and APB are defined and works for processor as system bus and peripheral bus respectively. The DMA controller functions between these two buses as a bridge and allow them to work concurrently. Depending on the speed of peripherals it uses buffering mechanism. Therefore an asynchronous FIFO is used for synchronizing the speed of peripherals. The proposed DMA controller can works in SoC along with processor and achieve fast data rate. The method introduced significant volume of data transfer with very low timing characteristics. Thus it is a better choice in respect of timing and volume of data. These two issues have been resolved under this research study. The results are compared with the AMD processors, like Geode GX 466, GX 500 and GX 533, and the presence and absence of DMA controller with processor is discussed and compared. The DMAC stands to be better alternative in SoC design.

show abstract

FPGA based High Speed Memory BIST Controller for Embedded Applications

Cited by 7 publications

References 6 publications

Global block level redundancy scheme for repair of clustered fault cells

Global block level redundancy scheme for repair of clustered fault cells

Memory test and repair technique for SoC based devices

Amba Based Advanced DMA Controller for SoC

Contact Info

Product

Resources

About