FPGA-Based Hardware Design for Scale-Invariant Feature Transform

Li, Shih‐An; Wang, Wei-Yen; Pan, Wei-Zheng; Hsu, Chen-Chien; Lu, Cheng-Kai

doi:10.1109/access.2018.2863019

Cited by 18 publications

(13 citation statements)

References 20 publications

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“…All these works have benefited from hardware parallelism offered by FPGAs to optimize the computation time and increase accuracy. But the developed architectures are dedicated to a very specific FPGA [2], [7], [8] and if you want to change the target FPGA card, you must make changes that can take a lot of time; as the example of [2] where architecture will be implemented on the FPGA of the Altera family. This paper presents a partial implementation of the SIFT algorithm, which is to implement just the extraction of the characteristics that is based on the LEON3 processor.…”

Section: Related Workmentioning

confidence: 99%

SIFT Implementation based on LEON3 Processor

Rashid¹,

Kaâniche²

2021

Adv. sci. technol. eng. syst. j.

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This paper proposes a new method of implementation of the part of SIFT (Scale-InvariantFeature Transform) algorithm used to extract the feature of an image of a size 256256 of pixels, which is mainly based on the using the LEON3 soft core processor .With this method it is possible to detect points of interest and so perform matching. This process allows several real time applications as robotic navigation, stereovision, object recognition etc. Obtained results show a very robustness in rotation, scale invariant as well as luminosity change. SIFT algorithm saw big success in various applications of computer vision. However, its high computation complexity has been a challenge for the most part of embedded implementations. This paper presents a partial implementation of the SIFT algorithm, which is to implement just the extraction of the characteristics that is based on the LEON3 processor. This implementation method overcomes the existing problems, in particular, the high dependence of existing implementations on the hardware architecture used. Indeed, the high flexibility of the processor allows the possibility to develop the application independent of the target board.

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Section: Related Workmentioning

confidence: 99%

SIFT Implementation based on LEON3 Processor

Rashid¹,

Kaâniche²

2021

Adv. sci. technol. eng. syst. j.

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“…In general, long latency is expected in constructing the multi-level Gaussian-blurred pyramids. Thus, as shown in Figure 2a, a more efficient structure had been proposed by simultaneously convoluting all the Gaussian functions, where suitable Gaussian kernels can be found by training the system with different images [12]. To further accelerate the construction of the DoG pyramid, a simplified structure is proposed in this paper, where new kernels for convolution are first derived by subtraction of two adjacent ones as shown in Figure 2b.…”

Section: Image Pyramidmentioning

confidence: 99%

“…That is, the detection point will have a high-contrast feature and could be regarded as a possible feature point when Equation (31) is satisfied. Since the condition for the high-contrast feature detection is less complicated than the conventional ones, the resulting hardware circuits will be simpler for achieving a higher operating speed [12].…”

Section: Corner Detectionmentioning

confidence: 99%

“…As a result, the efficiency of the subsequent mapping process could be limited. In [12], multiple levels of Gaussian-blurred images were simultaneously generated by adequately modifying Gaussian kernels to shorten the processing time, resulting in a frame rate of 150 fps for 640 × 480 images. Although a few dividers were only used by the modified approach for feature detection, the resulting 2 of 24 hardware cost is difficult to reduce because of the square function in the design.…”

Section: Introductionmentioning

confidence: 99%

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FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision

et al. 2021

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In this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangular identification approach with a look-up table is proposed to efficiently determine the direction and gradient of the feature points. Thus, the dimension of the feature descriptor in this paper is reduced by half compared to conventional approaches. As far as feature detection is concerned, the condition for high-contrast detection is simplified by moderately changing a threshold value, which also benefits the reduction of the resulting hardware in realization. The proposed enhanced-SIFT not only accelerates the operational speed but also reduces the hardware cost. The experiment results show that the proposed enhanced-SIFT reaches a frame rate of 205 fps for 640 × 480 images. Integrated with two enhanced-SIFT, a finite-area parallel checking is also proposed without the aid of external memory to improve the efficiency of feature matching. The resulting frame rate by the proposed stereo vision matching can be as high as 181 fps with good matching accuracy as demonstrated in the experimental results.

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“…The implementation of feature descriptors in the FPGAs remains an active research topic in recent years. Several works on fully pipelined FPGA accelerators for SIFT have been published since 2016 [30][31][32][33]. A parallel hardware architecture for SIFT was also reported in Reference [34].…”

Section: Comparison With Other Implementationsmentioning

confidence: 99%

Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA

2020

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Feature detection, description, and matching are crucial steps for many computer vision algorithms. These steps rely on feature descriptors to match image features across sets of images. Previous work has shown that our SYnthetic BAsis (SYBA) feature descriptor can offer superior performance to other binary descriptors. This paper focused on various optimizations and hardware implementation of the newer and optimized version. The hardware implementation on a field-programmable gate array (FPGA) is a high-throughput low-latency solution which is critical for applications such as high-speed object detection and tracking, stereo vision, visual odometry, structure from motion, and optical flow. We compared our solution to other hardware designs of binary descriptors. We demonstrated that our implementation of SYBA as a feature descriptor in hardware offered superior image feature matching performance and used fewer resources than most binary feature descriptor implementations.

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FPGA-Based Hardware Design for Scale-Invariant Feature Transform

Cited by 18 publications

References 20 publications

SIFT Implementation based on LEON3 Processor

SIFT Implementation based on LEON3 Processor

FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision

Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA

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