FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method)

Inam, Omair; Basit, Abdul; Qureshi, Mahmood; Omer, Hammad

doi:10.1016/j.compbiomed.2019.103598

Cited by 9 publications

(5 citation statements)

References 29 publications

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“…Li and Wyrwicz designed a single FPGA chip with a 2D Fast Fourier Transform (FFT) core to reconstruct multi-slice images without the need of additional hardware components [133]. More recently, different groups have presented FPGA designs intended to accelerate the MRI reconstruction through sensitivity encoding (SENSE) [134,135]. Thus, Inam et al obtained results that were comparable to those acquired with conventional CPU-based implementations but achieved lower computational time [135].…”

Section: Fpga In Medical Imagingmentioning

confidence: 99%

“…More recently, different groups have presented FPGA designs intended to accelerate the MRI reconstruction through sensitivity encoding (SENSE) [134,135]. Thus, Inam et al obtained results that were comparable to those acquired with conventional CPU-based implementations but achieved lower computational time [135]. Furthermore, FPGAs have been used for other MRI applications, such as spectrometry.…”

Section: Fpga In Medical Imagingmentioning

confidence: 99%

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Hardware Architectures for Real-Time Medical Imaging

et al. 2021

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Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of patients. Earlier prediction and treatment have been driving the acquisition of higher image resolutions as well as the fusion of different modalities, raising the need for sophisticated hardware and software systems for medical image registration, storage, analysis, and processing. In this scenario and given the new clinical pipelines and the huge clinical burden of hospitals, these systems are often required to provide both highly accurate and real-time processing of large amounts of imaging data. Additionally, lowering the prices of each part of imaging equipment, as well as its development and implementation, and increasing their lifespan is crucial to minimize the cost and lead to more accessible healthcare. This paper focuses on the evolution and the application of different hardware architectures (namely, CPU, GPU, DSP, FPGA, and ASIC) in medical imaging through various specific examples and discussing different options depending on the specific application. The main purpose is to provide a general introduction to hardware acceleration techniques for medical imaging researchers and developers who need to accelerate their implementations.

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Section: Fpga In Medical Imagingmentioning

confidence: 99%

Section: Fpga In Medical Imagingmentioning

confidence: 99%

Hardware Architectures for Real-Time Medical Imaging

et al. 2021

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“…The proposed solution is universal and allows one to speed up calculations in situations where there is limited computing power and time to perform the studies. This parallelization allows for an acceleration of calculations, for example, on GPU or FPGA [38][39][40][41][42], which is a current and much needed task. The special case of MultiPDF PF for N f = 1 is the simple bootstrap particle filter.…”

Section: Multipdf Particle Filtermentioning

confidence: 99%

MultiPDF particle filtering in state estimation of nonlinear objects

et al. 2021

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This paper presents a new particle filter algorithm (MultiPDF) for state estimation of nonlinear systems. The proposed method is a modification of the standard particle filter approach. Due to the strong need for the acceleration of calculations and an improvement in the estimation quality of state estimation, the authors propose a method which enables one to divide the main particle filter into smaller sub-filters with an accordingly smaller number of particles for each one of them. The algorithm has been implemented for various numbers of particles and subordinate parallel filters. Estimation quality has been checked for nine nonlinear objects (both one- and multidimensional) and evaluated through the quality index, average root-mean-squared error. The computation time of the particle filter algorithm for several hardware configurations has been compared. Based on the obtained results, it can be concluded that, besides the computation acceleration, the parallelization of the particle filter’s operation also improves the estimation quality.

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“…Recent studies have shown that the use of DL-based methods for image and signal processing in FPGAs has increased. The researchers in [ 32 ] proposed an FPGA-based acceleration method for parallel MRI reconstruction. As they noted, the computational requirements of MRI methods have increased to the point where using general-purpose computers for reconstruction would be impractically time consuming for real-time MRI.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Image Registration Using Accelerated CNN

Aydin

Bilge

2023

Sensors

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Background: Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention. Convolutional neural network (CNN)-based IR methods have resulted in applications that respond faster than traditional iterative IR methods. However, general-purpose processors are unable to operate at the maximum speed possible for real-time CNN algorithms. Due to its reconfigurable structure and low power consumption, the field programmable gate array (FPGA) has gained prominence for accelerating the inference phase of CNN applications. Methods: This study proposes an FPGA-based ultrasound IR CNN (FUIR-CNN) to regress three rigid registration parameters from image pairs. To speed up the estimation process, the proposed design makes use of fixed-point data and parallel operations carried out by unrolling and pipelining techniques. Experiments were performed on three US datasets in real time using the xc7z020, and the xcku5p was also used during implementation. Results: The FUIR-CNN produced results for the inference phase 139 times faster than the software-based network while retaining a negligible drop in regression performance of under 200 MHz clock frequency. Conclusions: Comprehensive experimental results demonstrate that the proposed end-to-end FPGA-based accelerated CNN achieves a negligible loss, a high speed for registration parameters, less power when compared to the CPU, and the potential for real-time medical imaging.

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FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method)

Cited by 9 publications

References 29 publications

Hardware Architectures for Real-Time Medical Imaging

Hardware Architectures for Real-Time Medical Imaging

MultiPDF particle filtering in state estimation of nonlinear objects

FPGA Implementation of Image Registration Using Accelerated CNN

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